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s d a 5 5 x x t v t e x t p r o e d i t i o n sept. 10, 2004 6 2 5 1 - 5 5 6 -3 d s d a t a s h e e t m i c r o n a s m i c r o n a s .com .com .com 4 .com u datasheet
sda 55xx data sheet 2 sept. 10, 2004; 6251-556-3ds micronas contents page section title 8 1. introduction 8 1.1. general features 8 1.1.1. external crystal and programmable clock speed 8 1.1.2. microcontroller features 9 1.1.3. memory 9 1.1.4. display features 9 1.1.5. acquisition features 9 1.1.6. ports 11 1.2. overview of current versions and packages for sda 55xx 12 2. functional description 12 2.1. clock system 12 2.1.1. general function 12 2.1.2. system clock 13 2.1.3. pixel clock 13 2.1.4. related registers 14 2.2. slicer and data acquisition 14 2.2.1. general function 14 2.2.2. slicer architecture 15 2.2.2.1. distortion processing 15 2.2.2.1.1. noise 15 2.2.2.1.2. frequency attenuation 15 2.2.2.1.3. group delay 15 2.2.2.2. data separation 15 2.2.3. h/v-synchronization 16 2.2.4. acquisition interface 16 2.2.4.1. framing code check 16 2.2.4.1.1. framing code fc1 16 2.2.4.1.2. framing code fcvps 16 2.2.4.1.3. framing code fc3 16 2.2.4.1.4. framing code fcwss 16 2.2.4.1.5. fc check select 16 2.2.4.2. interrupts 16 2.2.4.3. vbi buffer and memory organization 18 2.2.5. related registers 18 2.2.5.1. ram registers 18 2.2.5.1.1. field parameters 19 2.2.5.1.2. line parameters 19 2.2.6. recommended parameter settings 20 2.2.7. microcontroller 20 2.2.8. architecture 20 2.2.8.1. cpu hardware 20 2.2.8.1.1. instruction decoder 20 2.2.8.1.2. program control section 20 2.2.8.1.3. internal data ram 20 2.2.8.1.4. arithmetic/logic unit (alu) 21 2.2.8.1.5. boolean processor .com .com .com .com 4 .com u datasheet
contents, continued page section title data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 3 21 2.2.8.1.6. program status word register (psw) 21 2.2.8.1.7. stack pointer (sp) 22 2.2.8.1.8. data pointer register (dptr). 22 2.2.8.2. cpu timing 22 2.2.8.3. addressing modes 23 2.2.8.3.1. register addressing 23 2.2.8.3.2. direct addressing 23 2.2.8.3.3. register indirect addressing 23 2.2.8.3.4. immediate addressing 23 2.2.8.3.5. base register plus index register indirect addressing 23 2.2.9. ports and i/o-pins 25 2.2.9.1. read modify write feature 26 2.2.10. instruction set 26 2.2.10.1. notes on data addressing modes 26 2.2.10.2. notes on program addressing modes 27 2.2.10.3. instruction set description 32 2.2.10.4. instruction opcodes in hexadecimal order 37 2.3. interrupt 37 2.3.1. interrupt system 37 2.3.2. interrupt sources 37 2.3.3. overview 38 2.3.4. enabling interrupts 38 2.3.4.1. interrupt enable registers (ien0, ien1, ien2, ien3) 38 2.3.5. interrupt source registers 39 2.3.6. interrupt priority 39 2.3.6.1. interrupt priority registers (ip0 ip1) 40 2.3.7. interrupt vectors 41 2.3.8. interrupt and memory extension 41 2.3.9. interrupt handling 41 2.3.10. interrupt latency 41 2.3.11. interrupt flag clear 41 2.3.12. interrupt return 42 2.3.13. interrupt nesting 42 2.3.14. external interrupts 43 2.3.15. extension of standard 8051 interrupt logic 44 2.3.16. interrupt task function 44 2.3.17. power saving modes 44 2.3.18. power-save mode registers 45 2.3.19. idle mode 45 2.3.20. power-down mode 45 2.3.21. power-save mode 45 2.3.22. slow-down mode 46 2.4. reset 46 2.4.1. reset sources 46 2.4.2. reset filtering 46 2.4.3. reset duration 46 2.4.4. registers .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 4 sept. 10, 2004; 6251-556-3ds micronas contents, continued page section title 46 2.4.5. functional blocks 46 2.4.6. rams 46 2.4.7. analog blocks 46 2.4.8. microcontroller 46 2.4.9. ports 46 2.4.10. initialization phase 46 2.4.10.1. acquisition 46 2.4.10.2. display 47 2.5. memory organization 47 2.5.1. program memory 48 2.5.2. internal data ram 48 2.5.2.1. cpu ram 48 2.5.2.1.1. address space 48 2.5.2.1.2. registers 48 2.5.2.1.3. bit addressable ram area 48 2.5.2.1.4. stack 48 2.5.2.2. extended data ram (xram) 48 2.5.2.2.1. extended data memory address mapping 49 2.5.3. memory extension 49 2.5.3.1. memory extension registers 49 2.5.3.2. reset value 50 2.5.4. instructions on which memory extension would act 50 2.5.4.1. program memory banking (ljmp) 50 2.5.4.2. movc handling 50 2.5.4.2.1. movc with current bank 50 2.5.4.2.2. movc with memory bank 50 2.5.4.2.3. movx handling 50 2.5.4.2.4. movx with current bank 50 2.5.4.2.5. movx with data memory bank 50 2.5.4.3. calls and interrupts 50 2.5.4.3.1. memory extension stack 50 2.5.4.4. stack full 50 2.5.4.5. timing 50 2.5.4.6. interfacing extended memory 50 2.5.4.7. application examples 51 2.5.4.7.1. sample code 51 2.5.4.8. rom and romless version 51 2.6. uart 51 2.6.1. operation modes of the uart 51 2.6.1.1. mode 0 51 2.6.1.2. mode 1 51 2.6.1.3. mode 2 52 2.6.1.4. mode 3 52 2.6.2. multiprocessor communication 53 2.7. general purpose timers/counters 53 2.7.1. timer/counter 0: mode selection 53 2.7.1.1. mode 0 .com .com .com .com 4 .com u datasheet
contents, continued page section title data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 5 53 2.7.1.2. mode 1 53 2.7.1.3. mode 2 53 2.7.1.4. mode 3 53 2.7.2. timer/counter 1: mode selection 53 2.7.2.1. mode 2 53 2.7.2.2. mode 3 54 2.7.3. configuring the timer/counter input 54 2.7.4. timer/counter mode register 55 2.8. capture reload timer 55 2.8.1. input clock 55 2.8.2. reset values 55 2.8.3. functional description 55 2.8.3.1. port pin 55 2.8.3.2. slow down mode 55 2.8.3.3. run 55 2.8.3.4. overflow 55 2.8.3.5. modes 56 2.8.3.6. normal capture mode 56 2.8.3.7. polling mode 56 2.8.3.8. capture mode with spike suppression at the start of an infrared telegram 56 2.8.3.9. first event 56 2.8.3.10. second event 56 2.8.3.11. capture reload timer crt interrupt 57 2.8.3.12. counter stop 57 2.8.4. idle and power-down mode 57 2.8.5. registers 59 2.9. pulse width modulation unit 59 2.9.1. reset values 59 2.9.2. input clock 59 2.9.3. port pins 59 2.9.4. functional description 59 2.9.4.1. 8-bit pwm 60 2.9.4.2. 14-bit pwm 60 2.9.5. cycle time 61 2.9.6. power-down, idle and power-save mode 61 2.9.7. timer 62 2.9.8. control registers 63 2.10. watchdog timer 63 2.10.1. input clock 63 2.10.2. starting 63 2.10.3. refresh 63 2.10.4. wdt reset 63 2.10.5. power-down mode 63 2.10.6. time period 64 2.10.7. wdt as general purpose timer 65 2.11. analog digital converter (cadc) 65 2.11.1. power-down and wake-up .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 6 sept. 10, 2004; 6251-556-3ds micronas contents, continued page section title 65 2.11.2. registers 66 2.12. sync system 66 2.12.1. general description 66 2.12.1.1. screen resolution 66 2.12.1.1.1. blacklevel clamping area 66 2.12.1.1.2. border area 67 2.12.1.1.3. character display area 67 2.12.1.2. sync interrupts 68 2.12.1.3. related registers 69 2.13. display 69 2.13.1. display features 69 2.13.2. display memory 70 2.13.3. display memory 70 2.13.4. parallel character attributes 71 2.13.4.1. access of characters 71 2.13.4.2. address range from 0 d to 767 d 72 2.13.4.3. address range from 768 d to 1023 d 73 2.13.4.3.1. example 1 73 2.13.4.3.2. example 2 73 2.13.4.3.3. example 3 73 2.13.4.4. flash 73 2.13.4.4.1. flash for rom characters and 1-bit drcs characters 73 2.13.4.4.2. flash for 2-bit and 4-bit drcs characters 74 2.13.4.5. character individual double height 74 2.13.4.6. character individual double width 75 2.13.5. global osd attributes 79 2.13.6. character display area resolution 79 2.13.7. cursor 83 2.13.7.1. border color 83 2.13.7.2. full screen double height 85 2.13.7.3. flash rate control 86 2.13.7.4. transparency of boxes 88 2.13.7.5. clut 93 2.13.7.5.1. clut access for rom characters/1-bit drcs characters 93 2.13.7.5.2. clut access for 2-bit drcs characters 94 2.13.7.5.3. clut access for 4-bit drcs characters 94 2.13.7.6. character resolution 95 2.13.7.7. shadowing 96 2.13.7.8. progressive scan 96 2.13.8. drcs characters 96 2.13.8.1. memory organization of drcs characters 100 2.13.9. memory organization 102 2.13.9.1. character display area 102 2.13.9.2. clut area 102 2.13.9.3. global display word/cursor 102 2.13.9.4. 1-bit/2-bit/4-bit drcs character 103 2.13.9.5. overview on the sfr registers .com .com .com .com 4 .com u datasheet
contents, continued page section title data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 7 104 2.13.10. tvtext pro characters 109 2.14. d/a converter 109 2.14.1. related registers 110 3. special function register (sfr) 110 3.1. sfr register block index 110 3.2. sfr register index 114 3.3. sfr register address index 117 3.4. sfr register description 137 3.5. acq register block index 137 3.6. acq register index 138 3.7. acq register address index 139 3.8. acq register description 144 4. specifications 144 4.1. outline dimensions for psdip52-1 package 145 4.2. outline dimensions for psdip52-2 package 146 4.3. outline dimensions for pmqfp64-1 package 147 4.4. outline dimensions for plcc84-1 package 148 4.5. outline dimensions for pmqfp100-1 package 149 4.6. pin connections and short descriptions 155 4.7. port alternate functions 157 4.8. pin descriptions 159 4.9. pin configurations 163 4.10. electrical characteristics 163 4.10.1. absolute maximum ratings 164 4.10.2. recommended operating conditions 165 4.10.3. characteristics 169 4.10.4. timings 169 4.10.4.1. sync 170 4.10.4.2. program memory read cycle 171 4.10.4.3. data memory read cycle 172 4.10.4.4. data memory write cycle 173 4.10.4.5. blank/cor 174 5. applications 176 6. data sheet history .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 8 sept. 10, 2004; 6251-556-3ds micronas tvtext pro release note: revision bars indicate significant changes to the previous edition. 1. introduction the micronas sda 55xx tv microcontroller is dedi- cated to 8 bit applications for tv control and provides dedicated graphic features designed for modern low class to mid range tv sets. the sda 55xx is a microcontro ller and single chip tele- text decoder for decoding world system teletext data as well as other data services as video programming system (vps), program delivery control (pdc), and wide screen signalling (wss) data used for pal plus transmissions (in line 23). the data slicer and display part of the sda 55xx supports a wide range of tv standards including pal, ntsc as well as the acquisi- tion of the above mention data services as vps, wss, pdc, ttx and closed caption data. the slicer combined with its dedicated hardware stores ttx data in a vbi buffer of 1 kbyte. the micro- controller firmware available from micronas performs all the acquisition tasks (hamming and parity checks, page search and evaluation of header control bits) once per field. additionally, the firmware can provide high end teletext features like packet-26-handling, flof, top and list page mode. the application pro- gram interface (api) to the user software is optimized for a minimum sw overhead. the on-chip display unit used to display teletext data up to level 1.5 can also be used for customer defined on-screen displays (osd). the display generator is able to handle parallel display attributes, pixel oriented displays and dynamically re-definable characters (drcs). the sda 55xx provides also an integrated general- purpose, fully 8051-compatible microcontroller with specific hardware features especially suitable in tv sets. the microcontroller core has been enhanced to provide powerful features such as memory banking, data pointers and additional interrupts, etc. the internal xram consists of up to 16 kbytes. the microcontroller provides an internal rom of up to 128 kbytes. romless versions can access up to 1 mbyte of external ram and rom. the 8-bit microcontroller runs at 33.33 mhz internal clock. sda 55xx is realized in 0.25 micron technology with 2.5 v supply voltage for the core and 3.3 v for the i/o port pins to make them ttl compatible. based on the sda 55xx microcontroller the mints software package was developed and provides dedi- cated device drivers for many micronas video & audio products and includes a full blown tv control sw for the peper application chassis. the sda 55xx is also supported with powerful design tools like emulators from hitex, kleinhenz, isystems, the keil c51 com- piler and tedipro osd development sw by tara sys- tems. this support provided by micronas leads to: ? shorter time to market ? re-usability of the sw al so for future micronas products ? target independent sw development based on ansi c. ? verification and validation of sw before targeting and improved sw test concept ? graphical interface design requiring a minimum effort for osd programming and tv controlled know how. ? complete, modular and open tool chain available and configurable by customer. 1.1. general features ? 8051 compatible microcont roller with tv related special features and advanced osd display ? feature selection via special function register ? simultaneous processing of ttx, vps, pdc and wss (line 23) data ? supply voltage 2.5 v for core and 3.3 v for ports ? rom version package psdip52-2, pmqfp64-1 ? romless version package pmqfp100-2 ? 128 kbyte flash rom version package psdip52-2 1.1.1. external crystal and programmable clock speed ? normal mode 33.33 mhz cpu clock, power save mode 8.33 mhz ? cpu clock speed selectable via special function registers. ? single external 6 mhz crystal, all necessary clock signals are generated internally by means of plls 1.1.2. microcontroller features ? 8-bit 8051 instruction set compatible cpu ? two 16-bit timers ? watchdog timer ? capture compare timer for infrared remote control decoding ? pulse width modulation unit (2 channels 14 bit, 6 channels 8 bit) .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 9 ? adc (4 channels, 8 bit) ?uart 1.1.3. memory ? non-multiplexed 8-bit data and 16?20-bit address bus (romless version) ? memory banking up to 1 mbyte (romless version) ? up to 128 kbyte on-chip program rom ? eight 16-bit data pointer registers (dptr) ? 256-bytes on-chip processor internal ram (iram) ? 128 bytes extended stack memory ? display ram and txt/vps/pdc/wss data acqui- sition buffer directly accessible via movx command ? up to 16 kbyte on-chip extended ram (xram) con- sisting of 1 kbyte on-chip acq buffer ram (access via movx) 1 kbyte on-chip extended ram (xram, access via movx) for user software 3 kbyte display memory 1.1.4. display features ? rom character set supports all east and west euro- pean languages in a single device ? mosaic graphic character set ? parallel display attributes ? single/double width/height of characters ? variable flash rate ? programmable screen size (25 rows 1.1.5. acquisition features ? multistandard digital data slicer ? parallel multinorm slicing (ttx, vps, wss, cc, g+) ? four different framing codes available ? data caption only limited by available memory ? programmable vbi-buffer ? full channel data slicing supported ? fully digital signal processing ? noise measurement and controlled noise compen- sation ? attenuation measurement and compensation ? group delay measurement and compensation ? exact decoding of echo disturbed signals 1.1.6. ports ? one 8-bit i/o-port with open drain output and optional i 2 c bus emulation support (port 0) ? two 8-bit multifunction i/o-ports (port 1, port 3) ? one 4-bit port working as digital or analog inputs for the adc (port 2) ? one 2-bit i/o-port with secondary functions (p4.2, 4.3, 4.7) ? one 4-bit i/o-port with secondary function (p4.0, 4.1, 4.4) not available in psdip52-2) fig. 1?1: logic symbol tvt pro v cc v ss xtal1 xtal2 stop ene ocf cvbs ale psen r g b cor_bla hsync vsync rd wr address 20 bit data 8 bit port 0 8 bit port 1 8 bit port 2 4 bit port 3 6 bit port 4 6 bit rst cvbso cvbsi .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 10 sept. 10, 2004; 6251-556-3ds micronas fig. 1?2: block diagram memory extension unit m8051s core interrupt controller counter 1 counter 0 imran haj i musa hl iv ce peripheral bus interface iram 256x8 pwm capture control wdt memory extension stack 128x8 clock & sync system bus arbiter display generator clut dac's character rom 16kx8 blank/cor b r g v h adc acquisition slicer xram sram 16kx8bit program rom 128kx8 fifo acquisition interface adc interface ram/rom interface display logic display regs port logic uart analog mux a d c x 4 p[0 to 4] a[0 to 15] d[0 to 7] ale psen rd wr a[16 to a20] sfrs adc c v b s .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 11 1.2. overview of current versions and packages for sda 55xx table 1?1: tvtext pro versions and packages overview version type package sda 5550m ? romless version ? 16 kbyte ram pmqfp100-1 sda 5550 ? romless version ? 16 kbyte ram plcc84-1 sda 555xfl ? 128 kbyte flash memory on chip (re-pro- grammable) ? 16 kbyte ram psdip52-2 sda 555x x = 1...5 ? 32-128 kbyte user rom ? 8-16 kbyte ram pmqfp64-1, psdip52-1, psdip52-2 see note sda 5521 ? osd-only version ? 32 kbyte user rom on chip ? 8 kbyte ram psdip52-1, psdip52-2 see note sda 5522 ? osd-only version ? 64 kbyte user rom on chip ? 8 kbyte ram psdip52-1, psdip52-2 see note sda 5523 ? osd-only version ? 64 kbyte user rom on chip ? 16 kbyte ram psdip52-1, psdip52-2 see note sda 5525 ? osd only version ? 128 kbyte user rom on chip ? 16 kbyte ram psdip52-1, psdip52-2 see note sda 5577 ? standalone co-proce ssor for teletext reception, decoding, and display ? 10 pages ? rom fix-programmed with the software p116 psdip52-1, psdip52-2 see note note: micronas delivers two types of psdip52 packages (-1, -2). the packages have slightly different outline dimensions, but are considered identical. see outline dimensions for psdip52-1 package on page 144 and outline dimensions for psdip52-1 package on page 144. for logistics reasons, the customer cannot choose the package to be delivered. .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 12 sept. 10, 2004; 6251-556-3ds micronas 2. functional description 2.1. clock system 2.1.1. general function the on-chip clock generator provides the tvtpro with its basic clock signal. the o scillator runs with an exter- nal crystal and the appropriate internal oscillator cir- cuitry (see fig. on page 174). for applications with lower timing accuracy require- ments (and if the rtc is not used) an external ceramic resonator can be used. the usage of a ceramic reso- nator is not recommended for teletext applications as depending on the absolute tolerance of the ceramic resonator the data slicer may not work correctly. addi- tional this might also require that display timing param- eters and the baud rate prescaler have to be adapted. in timing critical applications the horizontal frequency of the incoming cvbs signal can be used to measure the actual timing deviation and to re-program the clock pll. the 6 mhz clock signal is used to generate the internal 300 mhz display reference clock by means of an on- chip phase locked loop (pll). the pll can be bypassed to reduce the power consumption. if an immediate wake up from power down is not required the pll can also be switched off in this mode. from the output frequency of the main clock pll two clock systems are derived. 2.1.2. system clock the 33.33 mhz system clock (f cpu ) is provided to the microcontroller core, all micr ocontroller related periph- erals, the sync timing logic, the a/d converters, the slicer, the display generator and the color lookup tables clut. it is possible to use 8.33 mhz (1/4 of 33.33 mhz) for the system clock domain (slow down mode). setting sfr-bit plls = 1 the user is able to send the pll into a power save mode. note: before the pll is switched to power save mode (plls = 1), the software has to switch the clock source from 200 mhz pll clock to the 3 mhz oscillator clock (sfr bit clk_src = 1). in this mode the slicer, acquisition, dac and display generator are switched off. to switch back to full frequency operation, the software has to end the pll power save mode (sfr-bit plls = 0), reset the pll for 10 fig. 2?1: clock system of tvtext pro osc pll dg uc uc-periph. ports sync adc slicer cluts dac 33.33 mhz 200 6 mhz f pix (10 .. 32mhz) xtpadin xtpadout dto display-fifo 300 mhz f sys or 8.33 or mhz 33.33 or pds or plls pll_res hin pf clke clk_src sd 8.33 mhz ext.clk 3mhz or : 2 : n oscclk or 33.33 3mhz or 66.67 6mhz pds .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 13 2.1.3. pixel clock the second clock system is the pixel clock (f pix ), which is programmable in a range from 10 ? 32 mhz. it serves the output part of the display fifo and the d/a converters. the pixel clock is derived from the high fre- quent output of the pll and line by line phase shifted to the positive edge of the horizontal sync signal (nor- mal polarity). because the final display clock is derived from a dto (digital time osc illator) it has no equidistant clock periods although the average frequency is exact. this pixel clock generation system has several advan- tages: ? the frequency of the pixel clock can be pro- grammed independently from the horizontal line period. ? because the input of the pll is already a signal with a relative high frequency, the resulting pixel fre- quency has an extremely low jitter. ? the resulting pixel clock follows the edge of the h- sync impulse without any delay and has always the same quality than the sync timing of the deflection controller. 2.1.4. related registers table 2?1: related registers and bits register name bit name 7 6 5 4 3 2 1 0 pclk1 pf[10:8] pclk0 pf[7:0] pcon smod pds idls sd gf1 gf0 pde idle psavex clk_src pll_res plls see section 3. on page 110 for detailed register description. .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 14 sept. 10, 2004; 6251-556-3ds micronas 2.2. slicer and data acquisition 2.2.1. general function tvtpro provides a full digital data slicer including digi- tal h- and v-sync separation and digital sync process- ing. the acquisition interface is capable to process all known data services transmitted in the vertical blank- ing interval vbi of a cvbs signal (teletext, vps, cc, g+, wss). four different framing codes (two of them freely programmable for each field) are available for each field. digital signal processing algorithms are applied to compensate various disturbing influences as there are: ? noise measurement and compensation. ? attenuation measurement and compensation. ? group delay measurement and compensation. note: tvtpro is optimized for precise data clock recovery and error free reception of data. thus, the reception of data services is widely unaf- fected by noise and the actual transmission channel characteristics. the cvbs input contains an on chip clamping circuit. the integrated a/d converter has a 7 bit resolution. the sampling frequency is 33.33 mhz. the sliced data are synchronized to the data clock fre- quency given by the clock-run-in. the framing code will define the start of the data stream. the resulting valid data will be written to the vbi data buffer. after line 23 is received an interrupt will be issued to the microcon- troller. the microcontroller starts processing the buff- ered data. that means, a sw module will check the data for errors and store them in an assigned memory area. to improve the data signal quality the slicer control logic generates horizontal and vertical windows during which the reception of the framing code is allowed. the framing code can be programmed individually for each line, so that in each line a different data service can be received. for vps and wss the framing code is hardwired. all following acquisition tasks are per- formed by the internal controller, so in principal the data of any data service can be acquired. 2.2.2. slicer architecture the slicer consists of three main blocks: ? the slicer ? the h/v synchronization for the slicer ? the acquisition interface fig. 2?2: block diagram of digital slic er and acquisition interface noise, attenuation, group-delay compensation noise, attenuation, group-delay measurement data separation d-pll address decoder parameter buffer acquisition interface cvbs h-pll sync separation h/v-sync separation to memory data slicer hs1_ir vs1_ir & timing l23_ir fc-check & ser/par converter cc_ir .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 15 2.2.2.1. distortion processing after a/d conversion the di gital cvbs bit stream is applied to internal circuitry which corrects the input signal for distortions created in the transmission chan- nel. in order to apply the right algorithm for the correc- tion, a signal measurement is done in parallel. this measurement unit can detect the following distortions. 2.2.2.1.1. noise the noise measurement unit incorporates two different algorithms. both algorithms use the value between two equalizing pulses, which corresponds to the black level. as the system knows the black level, a window is placed between this two equalizing pulses (located in line 4). the first algorithm compares successive the amplitude samples inside that window. the difference between these samples is measured and a flag is set as soon as this difference over several tv lines is greater than a specified value. this al gorithm is able to detect higher frequency noise (e.g. white noise). the second algorithm measures the difference between the black value and the actual sampled value inside this window. as soon as this difference over sev- eral tv lines is greater th an a specified value a second flag is set. this algorithm is sensitive against low fre- quency noise as it is known from co-channel distortion. both flags can be used to optimize the response of the compensation circuits in order to achieve best recep- tion performance. 2.2.2.1.2. frequency attenuation during signal transmission the cvbs signal can severely be attenuated. th is attenuation normally is frequency depending. that means that the higher the frequency the stronger the attenuation. as the clock run-in (from now on referred to as cri) for teletext rep- resents the highest possible frequency (3.5 mhz) it can be used to measure the attenuation. only strong negative attenuation causes problems during data slic- ing. a flag is needed to notify highly negative attenua- tion to the sw. if this flag is set a special peaking filter is switched on in the data-path. 2.2.2.1.3. group delay quite often the data stream is corrupted because of group delay distortion introduced by the transmission channel. the teletext framing code (e4 h ) is used as a measurement reference. the delay of the edges inside this code can be used to measure the group delay dis- tortion. the measurement is done during every teletext line and filtered over several lines. it can be detected whether the signal has positive, negative or no group delay distortions. two flags are set accordingly. by means of these two flags, an all- pass contained in the compensation circuit is config- ured to compensate positive or negative group delay. all of the above mentioned filters can be individually be disabled, set to forced mode, or automatic mode via control registers. 2.2.2.2. data separation parallel to signal analysis and distortion compensation another filter is calculatin g the required slicing level. the slicing level is the mean value of the clock run-in cri. as teletext is coded using the nrz format, the slicing level can not be calc ulated outside the cri tim- ing window and is therefore frozen after cri. using the found slicing level the data are sliced from the digitized cvbs signal. the result is a stream of zeros and ones. in order to find the logical zeros and ones which have been transmitted, the data clock needs to be recov- ered. therefore during the cri timing window a digital data pll (d-pll) is synchronized to the transitions in the sliced data stream which represent the original data clock. the frequency of the d-pll is also frozen after the cri timing window. timing information to freeze the slicing level, the d- pll and to control other actions are generated by the timing circuit. it generates also all control signals which have to be synchronized to the data start. 2.2.3. h/v-synchronization data slicer and acquisition interface require different control signals which have to be synchronized to the incoming cvbs (e.g. line number, field sequence or line start of a tv line). ther efore a slicing level for the sync pulses is calculated and the sync signal is sliced from the filtered digital cvbs signal. using a digital integrator vertical and horizontal sync pulses are separated. the horizontal pulses are fed into a digital h-pll which has flywheel functionality. the h-pll includes a counter which is used to gener- ate all the necessary horizontal control signals. the vertical sync pulse is used to synchronize the line counter, which generates the required vertical control signals. the synchronization block includes a watchdog for supervision of the actual lock condition of the h-pll. the watchdog can produce an interrupt (cc_ir) if syn- chronization has been lost. it could therefore be an indication for a channel change or missing input signal. .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 16 sept. 10, 2004; 6251-556-3ds micronas 2.2.4. acquisition interface the acquisition interface manages the data transfer from between slicer and memory. from slicer to mem- ory first of all a bit synchronization is performed (fram- ing code (fc) check). followin g this, the data is serial/ parallel converted. 8 bit wide words will be shifted into the memory. the data acquisition supports several fea- tures. the fc check is able to handle four different framing codes for one field. two of this framing codes are programmable and could therefore be changed from field to field. the acquisition can be switched from normal mode (line 6 to 23) to full channel mode (line 6 to the end of a field). in the other direction parameters are loaded from the memory to the slicer. this parameter down loading takes place after the vertical sync and after the hori- zontal sync. these parameters are used for the slicer configuration. 2.2.4.1. framing code check there are four framing codes fc implemented which are compared with the fc of the incoming signal. ? the first one is 8-bit wide and is loaded down with the field parameters. ? the second one is 16-bit wide and fixed to the fc of vps. ? the third one is 16-bit wide as well, but can be loaded with the field parameters. if the third one is used, the user can specify not only the fc but also a ?don?t-care? mask. ? the fourth fc is reserved for wss. the actual fc can be changed line by line. 2.2.4.1.1. framing code fc1 this fc should be used for all services with 8-bit fram- ing codes (e.g. for ttx). the actual framing code is loaded down each field. the check can be done with- out any bit error tolerance or with a tolerance of one bit. 2.2.4.1.2. framing code fcvps this fc is fixed to that of vps. only an error-free sig- nal will enable the reception of the vps data line. note: if vps should be sliced in field 1 and ttx in field 2, the appropriate line parameters for line 16 have to be changed dynamically from field to field. 2.2.4.1.3. framing code fc3 this 16-bit fc is loaded with the field parameters as well as a ?don?t care? ma sk. the incoming signal is compared with both, the framing code and the ?don?t care? mask. further recepti on is enabled if all bits which are not ?don?t care? match the incoming data stream. 2.2.4.1.4. framing code fcwss this fc is pre-programmed to that of wss. only an error-free signal will enable the reception of the wss data line. 2.2.4.1.5. fc check select there is a two bit line parameter called fcsel. by means of this parameter the user is able to select which fc check is used for the actual line. if norm is set to wss the wss fc check is used independently of fcsel. 2.2.4.2. interrupts some events which occur inside the slicer, sync sepa- ration or acquisition interface should cause an inter- rupt. they are summarized in register cisr0 and cisr1 . the slicer hardware sets the related interrupt flag which must be reset by the application software before the next interrupt can be accepted. 2.2.4.3. vbi buffer and memory organization the implemented sw has to provide configuration parameters for the slicer an d the acquisition interface. both circuits will produce st atus information for the cpu. some of these parameters and status bits are constant during the duration of a field. those parameters are called field parameters. they are downloaded after the vertical sync. other parameters and status bits may change from line to line (e.g. data service depending values). those parameters are called line parameters. they are down- loaded after each horizontal sync impulse. the start address of the vbi buffer can be configured with a special function register ? strvbi ?. 9 bytes are needed for the field parameter. 47 bytes should be reserved for every sliced data line. if 18 lines of data (in full channel mode 314) have been send to memory no further data acquisition will take place until the next vertical pulse appears a nd the h-pll is still locked. .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 17 that means if at least 855 bytes (14767 bytes in full channel mode) are reserved for the vbi buffer size in the ram no vbi overflow will occur. the controller can start or stop the vbi data acquisition using bit ?acqon? of register strvbi . the acquisition is stopped as soon as this bit is changed to ?0?. if the bit is changed back to ?1? the ac quisition starts again with the next v-pulse (only if stab = 1). the start address (bit 3 ? 0 of register strvbi ) of the vbi buffer should only be changed if the acquisition is switched off. fig. 2?3: vbi buffer: general structure 0 7 acqfp0 acqfp1 acqfp2 acqfp3 acqfp4 acqfp5 send to slicer after v-pulse write to memory after v-pulse strvbi acqlp0 acqlp1 send to slicer after h-pulse send to memory send to slicer after h-pulse acqlp0 acqlp1 data byte 41 acqlp2 acqfp6 field parameters field status information line parameters field parameters field parameters field parameters field parameters field parameters field status information field status information acqfp7 acqfp8 line parameters line parameters line parameters acqlp3 line status data byte 1 data byte 0 data byte 2 line parameters line parameters line parameters line parameters line status data byte 0 data byte 1 data byte 2 vbi start line 6 acqlp4 acqlp2 acqlp3 acqlp4 send to memory data byte 41 47 byte and so on (until line 23 has been stored) .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 18 sept. 10, 2004; 6251-556-3ds micronas 2.2.5. related registers the acquisition interface has only three sfr regis- ters. the line and field parameters are stored in the ram (ram registers). they have to be initialized by software before starting the data acquisition. 2.2.5.1. ram registers see section 3. on page 110 for detailed register description. 2.2.5.1.1. field parameters all field parameters are updated once in a field. that means the status information written from the acquisi- tion interface to the memory represents only a snap- shot of the status. table 2?2: related registers register name bit name 7 6 5 4 3 2 1 0 strvbi acqon reserved acqsta vbiadr cisr0 bit addressable l24 adc wtmr avs dvs pwtmr ahs dhs cisr1 bit addressable cc adw iex[1:0] see section 3. on page 110 for detailed register description. table 2?3: field parameters register name bit name 7 6 5 4 3 2 1 0 acqfp0 fc3[15:8] acqfp1 fc3[7:0] acqfp2 fc3mask[15:8] acqfp3 fc3mask[7:0] acqfp4 fc1[7:0] acqfp5 agdon afron anoon gdpon gdnon freon noion full acqfp6 noise(0) freattf stab vdok field noise(1) grdon grdsign acqfp7 leofli[11:8] acqfp8 leofli[7:0] see section 3. on page 110 for detailed register description. .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 19 2.2.5.1.2. line parameters 2.2.6. recommended parameter settings table 2?4: line parameters register name bit name 7 6 5 4 3 2 1 0 acqlp0 dincr[15:8] acqlp1 dincr[7:0] acqlp2 norm[2:0] fcsel[1:0] fc1er vcr reserved acqlp3 mlength[2:0] alength[1:09 clkdiv[2:0] acqlp4 perr[5:0] tlde fcok see section 3. on page 110 for detailed register description. table 2?5: recommended parameter settings ttx vps wss cc g+ agdon 10000 afron 10000 anoon11111 gdpon00000 gdnon00000 freon 00000 noion 00000 dincr 54559 39321 39321 7920 7920 fc1e 00000 mlength12777 alength 2 2 2 2 2 clkdiv 00255 norm 0 2 3 4 5 fcsel 01222 vcr 00000 match 00000 fc1 228 don?t care don?t care don?t care don?t care fc3 don?t care don?t care don?t care 3 1261 fc3mask don?t care don?t care don?t care 65472 63488 .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 20 sept. 10, 2004; 6251-556-3ds micronas 2.2.7. microcontroller 2.2.8. architecture every cpu machine cycle consists of 12 internal cpu clock periods. the cpu manipulates operands in two memory spaces: the program memory space, and the data memory space. the program memory address space is provided to accommodate relocatable code. the data memory address space is divided into the 256-byte internal data ram, xram (extended data memory, accessible with movx instructions) and the 128-byte special function register (sfr) address space. four register banks (each bank has eight registers), 128 addressable bits, and the stack reside in the inter- nal data ram. the stack depth is limited only by the available internal data ram. its location is determined by the 8-bit stack pointer. all registers except the pro- gram counter and the four 8-register banks reside in the special function register address space. these memory mapped registers include arithmetic registers, pointers, i/o-ports, registers for the interrupt system, timers, pulse width modulator, capture control unit, watchdog timer, uart, display, acquisition control etc. many locations in the sfr address space are bit- wise addressable. note: reading from unused locations within data memory will yield undefined data. conditional branches are performed relative to the 16 bit program counter. the register indirect jump per- mits branching relative to a 16-bit base register with an offset provided by an 8-bit index register. sixteen-bit jumps and calls permit branching to any location in the memory address space. the microcontroller has five methods for addressing source operands: register, direct, register-indirect, immediate, and base register plus index register-indi- rect addressing. the first three methods can be used for addressing destination operands. most instructions have a ?desti- nation, source? field that specifies the data type, addressing methods and operands involved. for oper- ations other than moves, the destination operand is also a source operand. registers in the four 8-register banks can be accessed through register, direct, or register-indirect addressing. the lower 128 bytes of internal data ram can be accessed through direct or register-indirect address- ing, the upper 128 bytes of internal data ram through register-indirect addressing; and the special function registers through direct addressing. look-up tables resident in program memory can be accessed through base register plus index register-indirect addressing. 2.2.8.1. cpu hardware 2.2.8.1.1. instruction decoder each program instruction is decoded by the instruction decoder. this unit generates the internal signals that control the functions of each unit within the cpu sec- tion. these signals control the sources and destination of data, as well as the function of the arithmetic/logic unit (alu). 2.2.8.1.2. program control section the program control section controls the sequence in which the instructions stor ed in the program memory are executed. the conditional branch logic enables conditions internal and external to the microcontroller to cause a change in the sequence of program execu- tion. the 16-bit program counter holds the address of the instruction to be executed. it is manipulated with the control transfer instructions listed in section 2.2.10.. 2.2.8.1.3. internal data ram the internal data ram provides a 256-byte scratch pad memory, which includes four register banks and 128 direct addressable software flags. each register bank contains registers r0 ? r7. the addressable flags are located in the 16-byte locations starting at byte address 20 h and ending with byte location 2f h of the ram address space. in addition to this standard internal data ram the microcontroller contains an extended internal ram. it can be considered as a part of an external data mem- ory. it is referenced by movx instructions (movx a, @dptr), the memory organization is explained in section 2.5. on page 47. 2.2.8.1.4. arithmetic/logic unit (alu) the arithmetic section of the microcontroller performs many data manipulation functions and includes the arithmetic/logic unit (alu) and the acc , b , and psw registers. the alu accepts 8-bit data words from one or two sources and generates an 8-bit result under the control of the instruction decoder. the alu performs the arithmetic operations of add, subtract, multiply, divide, increment, decrement, bcd-decimal-add adjust and compare, and the logic operations like and, or, .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 21 exclusive-or, complement and rotate (right, left, or nib- ble swap). the register acc is the accumulator, the register b is dedicated during multiply and divide and serves as both source and destination. during all other opera- tions the register b is simply another location of the special function register space and may be used for any purpose. 2.2.8.1.5. boolean processor the boolean processor is an integral part of the micro- controller architecture. it is an independent bit proces- sor with its own instructio n set, its own accumulator (the carry flag) and its own bit-addressable ram and i/ o. the bit manipulation in structions allow the direct addressing of 128 bits within the internal data ram and several bits within the special function registers. the special function registers which have addresses exactly divisible by eight contain directly addressable bits. the boolean processor can perform, on any address- able bit, the bit operations of ?set?, ?clear?, ?comple- ment?, ?jump-if-set?, ?jump-if-not-set?, ?jump-if-set then- clear? and ?move to/from carry?. between any address- able bit (or its complement) and the carry flag it can perform the bit operation of logical and or logical or with the result returned to the carry flag. 2.2.8.1.6. program status word register (psw) the psw flag bits record microcontroller status infor- mation and control the operation of the microcontroller. the carry (cy), auxiliary carry (ac), two user flags (f0 and f1), register bank select (rs0 and rs1), overflow (ov) and parity (p) flags reside in the program status word register. these flags are bit-memory-mapped within the byte-memory-mapped psw . the cy, ac, and ov flags generally reflect the status of the latest arithmetic operations. the cy flag is also the boolean accumulator for bit operations. the p-flag always reflects the parity of the register acc . f0 and f1 are general purpose flags which are pushed onto the stack as part of a psw save (see table 2?7). the two register bank select bits (rs1 and rs0) deter- mine which one of the four register banks is selected as show in table 2?6. see section 3. on page 110 for detailed register description. 2.2.8.1.7. stack pointer (sp) the 8-bit stack pointer contains the address at which the last byte was pushed onto the stack. this is also the address of the next by te that will be popped. the sp is incremented during a push. sp can be read or written to under software control. the stack may be located anywhere within the internal data ram address space and may be as large as 256 bytes. note: for memory above 64k, the memory extension stack is used, refer to section 2.5.3. on page 49. table 2?6: register banks rs1 rs0 register bank register location 0 0 1 1 0 1 0 1 0 1 2 3 00 h ?07 h 08 h ?0f h 10 h ?17 h 18 h ?1f h table 2?7: related register register name bit name 7 6 5 4 3 2 1 0 psw cy ac f0 rs[1:0] ov f1 p see section 3. on page 110 for detailed register description. .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 22 sept. 10, 2004; 6251-556-3ds micronas 2.2.8.1.8. data pointer register (dptr) . the 16-bit data pointer register dptr is the concate- nation of registers dph (high-order byte) and dpl (low-order byte). the dptr is used in register-indirect addressing to move program memory constants and to access the extended data memory. dptr may be manipulated as one 16-bit register or as two indepen- dent 8-bit registers dpl and dph . eight data pointer registers are available, the active one is selected by a special function register ( dpsel ) 2.2.8.2. cpu timing timing generation is completely self-contained, except for the frequency reference which can be a crystal or external clock source. the on-board oscillator is a par- allel anti-resonant circuit. the xtal2 pin is the output of a high-gain amplifier, wh ile xtal1 is its input. a crystal connected between xtal1 and xtal2 pro- vides the feedback and phase shift required for oscilla- tion. in slowdown mode, the microcontroller runs at one fourth the normal frequency. this mode is useful when power consumption needs to be reduced. slow down mode is entered by setting the bit sd in pcon regis- ter. note: any slow-down mode should only be used if teletext reception and the display are disabled. otherwise processing of the incoming text data might be incomplete and the display structure will be corrupted. for disabling acquisition and display generator see section 2.3.17. 2.2.8.3. addressing modes there are five general addressing modes operating on bytes. one of these five addressing modes, however, operates on both bytes and bits: ?register ? direct (both bytes and bits) ? register indirect ? immediate ? indirect, using base register plus index-register the following list summarizes, which memory spaces may be accessed by each of the addressing modes: register addressing r0 ? r7 acc , b , cy (bit), dptr direct addressing ram (low part) special function registers register-indirect addressing ram (@r1, @r0, sp ) immediate addressing program memory base register plus i ndex-register indirect addressing program memory (@dptr + a, @pc + a) table 2?8: related registers register name bit name 7 6 5 4 3 2 1 0 dpl dpl[7:0] dph dph[7:0] dpsel dpsel[2:0] see section 3. on page 110 for detailed register description. .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 23 2.2.8.3.1. register addressing register addressing accesses the eight working regis- ters (r0 ? r7) of the selected register bank. the psw register flags rs1 and rs0 determine which reg- ister bank is enabled. the least significant three bits of the instruction opcode indicate which register is to be used. acc , b , dptr and cy, the boolean processor accumulator, can also be addressed as registers. 2.2.8.3.2. direct addressing direct byte addressing specifies an on-chip ram loca- tion (only low part) or a special function register. direct addressing is the only method of accessing the special function registers. an additional byte is appended to the instruction opcode to provide the memory location address. the highest order bit of this byte selects one of two groups of addresses: values between 00 h ?7f h access internal ram locations, while val- ues between 80 h ?0ff h access one of the special function registers. 2.2.8.3.3. register indirect addressing register indirect addressing uses the contents of either r0 or r1 (in the selected register bank) as a pointer to locations in the 256 bytes of internal ram. note that the special function registers are not acces- sible by this method. execution of push and pop instructions also use reg- ister-indirect addressing. the stack pointer may reside anywhere in internal ram. 2.2.8.3.4. immediate addressing immediate addressing allows constants to be part of the opcode instruction in program memory. an additional byte is app ended to the instruction to hold the source variable. in the assembly language and instruction set, a number sign (#) precedes the value to be used, which may refer to a constant, an expression, or a symbolic name. 2.2.8.3.5. base register plus index register indi- rect addressing base register plus index register indirect addressing allows a byte to be accessed from program memory via an indirect move from the location whose address is the sum of a base register (dptr or pc) and index register, acc . this mode facilitates accessing to look- up table resident in program memory. 2.2.9. ports and i/o-pins there are 34 port pins available, out of which 24 are i/ o pins configured as three 8-bit wide ports p0, p1, and p3. port 4 consists of 6 i/o bits, out of which only 3 are available in the psdip52-2 package. all 6 port pins are only available in the other packages with higher pin count. each pin can be individually and independently programmed as input or output and each can be con- figured dynamically. one 4-bit-port p2 is input only. an instruction that uses a port's bit/byte as a source operand reads a value that is the logical and of the last value written to the bit/byte and the polarity being applied to the pin/pins by an external device (this assumes that none of the microcontroller's electrical specifications are being violated). an instruction that reads a bit/byte, operates on the content, and writes the result back to the bit/byte, reads the last value written to the bit/byte instead of the logic level at the pin/pins. pins of a single port can be individually configured as inputs and outputs by writing a ?one? to each pin that is to be an input. each time an instruction uses a com- plete port as destination, the sw has to make sure that ?ones? are written to those bits that correspond to the pins used as inputs. an external input signal to a port pin needs not to be synchronized to the internal clock. all the port latches have ?one? s written to them by the reset function. if a ?zero? is subsequently written to a port latch, it can be reconfigured as an input by writing a ?one? to it. the instructions that perform a read of, operation on, and write to a port?s bit/bytes are inc, dec, cpl, jbc, setb, clr, mov p.x, cjne, djnz, anl, orl, and xrl. the data read by these instructions is the last value that was written to the port, without regard to the levels being applied at the pins. this insures that bits written to a ?one? (for use as inputs) are not inadvert- ently cleared. port 0 has an open-drain output. writing a ?one? to the bit latch leaves the output transistor off, so the pin floats. in that condition it can be used as a high-impedance input. port 0 is considered ?true bidirectional?, because when configured as an input it floats. ports 1, 3 and 4 have ?quasi-bidirectional? output driv- ers. in ports p1, p3 and p4 the output drivers provide source current for one system clock period if, and only if, software updates the bit in the output latch from a ?zero? to an ?one?. sourcing current only on ?zero to one? transition prevents a pin, programmed as an input, .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 24 sept. 10, 2004; 6251-556-3ds micronas from sourcing current into the external device that is driving the input pin. it is not allowed to drive port 3.6 to logic low level while reset state changes from the active to inactive state otherwise a special test mode is activated. secondary functions can be selected individually and independently for the pins of port 1 and 3. further information on port 1's secondary functions is given in section 2.9. on page 59 . p3 generates the secondary control signals automatically as long as the pin corre- sponding to the appropriate signal is programmed as an input, i. e. if the corresponding bit latch in the p3 special function register contains a ?one?. table 2?9: ports and i/o-pins port i/o default function alternate function 2 alternate function 3 toggle function toggle function control bit function control bit function p0(0?7) i/o port pin ? ? ? ? p1(0) i/o port pin pwme(e0) pwm 8 bit channel 0 ? ? p1(1) i/o port pin pwme(e1) pwm 8 bit channel 1 ? ? p1(2) i/o port pin pwme(e2) pwm 8 bit channel 2 ? ? p1(3) i/o port pin pwme(e3) pwm 8 bit channel 3 ? ? p1(4) i/o port pin pwme(e4) pwm 8 bit channel 4 ? ? p1(5) i/o port pin pwme(e5) pwm 8 bit channel 5 ? ? p1(6) i/o port pin pwme(e6) pwm 14 bit channel 0 ? ? p1(7) i/o port pin pwme(e7) pwm 14 bit channel 1 ? ? p2(0) i port pin cadcco(ad0) adc channel 0 ? ? p2(1) i port pin cadcco(ad1) adc channel 1 ? ? p2(2) i port pin cadcco(ad2) adc channel 2 ? ? p2(3) i port pin cadcco(ad3) adc channel 3 ? ? p3(0) i/o port pin cscr0(o_e_p3_0 ) odd/even indicator ? ? p3(1) i/o port pin port input mode external extra int 0 port output mode txd p3(2) i/o port pin port input mode external interrupt 0 ? ? p3(3) i/o port pin port input mode external interrupt 1 ? ? p3(4) i/o port pin port input mode timer/counter 0 input ? ? p3(5) i/o port pin port input mode timer/counter 1 input ? ? p3(6) i/o port pin ? ? ? ? p3(7) i/o port pin port input mode external extra int 1 port input mode rxd p4(0) 1) i/o a17 cscr1(a17 _p4_0) port pin ? ? 1) not available in psdip52-2 .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 25 2.2.9.1. read modify write feature ?read-modify-write? commands are instructions that read a value, possibly change it, and then rewrite it to the latch. the read-modify-write instructions are listed in table 2?10. if the destination operand is a port or a port bit, these instructions read the information stored in the latch rather than the status of the pin. the read-modify-write instructions are directed to the latch rather than to the pin in order to avoid a possible misinterpretation of the voltage level at the pin. for example, a port bit might be used to drive the base of a transistor. if a ?one? is written to the bit, the transistor is turned on. if the cpu would read back the status of the same port bit from the pin rather than the latch, it would read the base-emitter voltage of the transistor and interpret it as a logic ?0?. reading the latch rather than the pin will return the correct value of logic ?1?. p4(1) 1) i/o a18 cscr1(a18 _p4_1) port pin ? ? p4(2) i/o port pin cscr1(enarw) read signal ? ? p4(3) i/o port pin cscr1(enarw) write signal ? ? p4(4) 1) i/o a19 cscr1(a19 _p4_4) port pin ? ? p4(7) i/o port/vs in cscr0(vs_oe , p4_7 _alt) vs output cscr0 (vs_oe , p4_7 _alt) oddeven out- put 1) not available in psdip52-2 table 2?9: ports and i/o-pins, continued port i/o default function alternate function 2 alternate function 3 toggle function toggle function control bit function control bit function table 2?10: read-modify-write instructions mnemonic description example anl orl xrl jbc cpl inc dec djnz mov px.y, c 1) clr px.y 1) set px.y 1) logical and logical or logical ex ? or jump if bit = 1 and clear bit complement bit increment decrement decrement and jump if not zero move carry bit to bit y of port x clear bit y of port x set bit y of port x anl p1, a orl p2, a xrl p3, a jbc p1.1, label cpl p3.0 inc p1 dec p1 djnz p3, label mov p1.7, c clr p2.6 set p3.5 1) the instruction reads the port byte (all 8 bits), modifies the addressed bit, then writes the new byte back to the latch. .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 26 sept. 10, 2004; 6251-556-3ds micronas 2.2.10. instruction set the assembly language uses the same instruction set and the same instruction opcodes as the 8051 micro- computer family. 2.2.10.1. notes on data addressing modes rn ? working register r0 - r7. direct ? 128 internal ram-locations, any i/o- port, control or status register. @ri ? indirect internal ram-location addressed by register r0 or r1. #data ? 8-bit constant included in instruction. #data 16 ? 16-bit constant included as bytes 2 & 3 of instruction. bit ? 128 software flags, any i/o-pin, control or status bit in special function registers. operations working on external data memory (movx ?) are used to access the extended internal data ram (xram). 2.2.10.2. notes on program addressing modes addr 16 ? destination address for lcall & ljmp may be anywhere within the program memory address space. addr 11 ? destination address for acall & ajmp will be within the same 2 kbyte of the following instruction. rel ? sjmp and all conditional jumps include an 8-bit offset byte. range is +127/-128 bytes relative to first byte of the follow- ing instruction. .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 27 2.2.10.3. instruction set description table 2?11: arithmetic operations mnemonic description byte add a, rn add register to accumulator 1 add a, direct add direct byte to accumulator 2 add a, @ri add indirect ram to accumulator 1 add a, #data add immediate data to accumulator 2 addc a, rn add register to accumulator with carry flag 1 addc a, direct add direct byte to a with carry flag 2 addc a, @ri add indirect ram to a with carry flag 1 addc a, #data add immediate data to a with carry flag 2 subb a, rn subtract register from a with borrow 1 subb a, direct subtract direct byte from a with borrow 2 subb a, @ri subtract indirect ram from a with borrow 1 subb a, #data subtract immediate data from a with borrow 2 inc a increment accumulator 1 inc rn increment register 1 inc direct increment direct byte 2 inc @ri increment indirect ram 1 dec a decrement accumulator 1 dec rn decrement register 1 dec direct decrement direct byte 2 dec @ri decrement indirect ram 1 inc dptr increment data pointer 1 mul ab multiply a & b 1 div ab divide a & b 1 da a decimal adjust accumulator 1 .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 28 sept. 10, 2004; 6251-556-3ds micronas table 2?12: logical operations mnemonic description byte anl a, rn and register to accumulator 1 anl a, direct and direct byte to accumulator 2 anl a, @ri and indirect ram to accumulator 1 anl a, #data and immediate data to accumulator 2 anl direct, a and accumulator to direct byte 2 anl direct, #data and immediate data to direct byte 3 orl a, rn or register to accumulator 1 orl a, direct or direct byte to accumulator 2 orl a, @ri or indirect ram to accumulator 1 orl a, #data or immediate data to accumulator 2 orl direct, a or accumulator to direct byte 2 orl direct, #data or immediate data to direct byte 3 xrl a, rn exclusive-or register to accumulator 1 xrl a, direct exclusive-or direct byte to accumulator 2 xrl a, @ri exclusive-or indirect ram to accumulator 1 xrl a, #data exclusive-or immediate data to accumulator 2 xrl direct, a exclusive-or accumulator to direct byte 2 xrl direct, #data exclusive-or immediate data to direct 3 clr a clear accumulator 1 cpl a complement accumulator 1 rl a rotate accumulator left 1 rlc a rotate a left through the carry flag 1 rr a rotate accumulator right 1 rrc a rotate a right through carry flag 1 swap a swap nibbles within the accumulator 1 .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 29 table 2?13: boolean variable manipulation mnemonic description byte clr c clear carry flag 1 clr bit clear direct bit 2 setb c set carry flag 1 setb bit set direct bit 2 cpl c complement carry flag 1 cpl bit complement direct bit 2 anl c, bit and direct bit to carry flag 2 anl c, /bit and complement of direct bit to carry 2 orl c, bit or direct bit to carry flag 2 orl c, /bit or complement of direct bit to carry 2 mov c, bit move direct bit to carry flag 2 mov bit, c move carry flag to direct bit 2 .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 30 sept. 10, 2004; 6251-556-3ds micronas table 2?14: data transfer operations mnemonic description byte mov a, rn move register to accumulator 1 mov a, direct move direct byte to accumulator 2 mov a, @ri move indirect ram to accumulator 1 mov a, #data move immediate data to accumulator 2 mov rn, a move accumulator to register 1 mov rn, direct move direct byte to register 2 mov rn, #data move immediate data to register 2 mov direct, a move accumulator to direct byte 2 mov direct, rn move register to direct byte 2 mov direct, direct move direct byte to direct 3 mov direct, @ri move indirect ram to direct byte 2 mov direct, #data move immediate data to direct byte 3 mov @ri, a move accumulator to indirect ram 1 mov @ri, direct move direct byte to indirect ram 2 mov @ri, #data move immediate data to indirect ram 2 mov dptr, #data 16 load data pointer with a 16-bit constant 3 movc a@a + dptr move code byte relative to dptr to accumulator 1 movc a@a + pc move code byte relative to pc to accumulator 1 movx a, @ri move external ram (8-bit addr) to accumulator 1) 1 movx a, @dptr move external ram (16-bit addr) to accumulator 1 movx @ri, a move a to external ram (8-bit addr) 1) 1 movx @dptr, a move a to external ram (16-bit addr) 1 push direct push direct byte onto stack 2 pop direct pop direct byte from stack 2 xch a, rn exchange register with accumulator 1 xch a, direct exchange direct byte with accumulator 2 xch a, @ri exchange indirect ram with accumulator 1 xchd a, @ri exchange low-order digital indirect ram with a 1) 1 1) not applicable .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 31 table 2?15: program and machine control operations mnemonic description byte acall addr 11 absolute subroutine call 2 lcall addr 16 long subroutine call 3 ret return from subroutine 1 reti return from interrupt 1 ajmp addr 11 absolute jump 2 ljmp addr 16 long jump 3 sjmp rel short jump (relative addr) 2 jmp @a + dptr jump indirect relative to the dptr 1 jz rel jump if accumulator is zero 2 jnz rel jump if accumulator is not zero 2 jc rel jump if carry flag is set 2 jnc rel jump if carry flag is not set 2 jb bit, rel jump if direct bit set 3 jnb bit, rel jump if direct bit not set 3 jbc bit, rel jump if direct bit is set and clear bit 3 cjne a, direct rel compare direct to a and jump if not equal 3 cjne a, #data, rel compare immediate to a and jump if not equal 3 cjne rn, #data, rel compare immediate to register and jump if not equal 3 cjne @ri, #data, rel compare immediate to indirect and jump if not equal 3 djnz rn, rel decrement regist er and jump if not zero 2 djnz direct, rel decrement dire ct and jump if not zero 3 nop no operation 1 .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 32 sept. 10, 2004; 6251-556-3ds micronas 2.2.10.4. instruction opcodes in hexadecimal order table 2?16: instruction opcodes in hexadecimal order hex code number of bytes mnemonic operands 00 1 nop ? 01 2 ajmp code addr 02 3 ljmp code addr 03 1 rr a 04 1 inc a 05 2 inc data addr 06 1 inc @r0 07 1 inc @r1 08 1 inc r0 09 1 inc r1 0a 1 inc r2 0b 1 inc r3 0c 1 inc r4 0d 1 inc r5 0e 1 inc r6 0f 1 inc r7 10 3 jbc bit addr, code addr 11 2 acall code addr 12 3 lcall code addr 13 1 rrc a 14 1 dec a 15 2 dec data addr 16 1 dec @r0 17 1 dec @r1 18 1 dec r0 19 1 dec r1 1a 1 dec r2 1b 1 dec r3 1c 1 dec r4 1d 1 dec r5 1e 1 dec r6 1f 1 dec r7 20 3 jb bit addr, code addr 21 2 ajmp code addr 22 1 ret ? 23 1 rl a 24 2 add a, #data 25 2 add a, data addr 26 1 add a, @r0 27 1 add a, @r1 28 1 add a, r0 29 1 add a, r1 2a 1 add a, r2 2b 1 add a, r3 2c 1 add a, r4 2d 1 add a, r5 2e 1 add a, r6 2f 1 add a, r7 30 3 jnb bit addr, code addr 31 2 acall code addr 32 1 reti ? 33 1 rlc a 34 2 addc a, #data 35 2 addc a, data addr 36 1 addc a, @r0 37 1 addc a, @r1 38 1 addc a, r0 39 1 addc a, r1 table 2?16: instruction opcodes in hexadecimal order hex code number of bytes mnemonic operands .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 33 3a 1 addc a, r2 3b 1 addc a, r3 3c 1 addc a, r4 3d 1 addc a, r5 3e 1 addc a, r6 3f 1 addc a, r7 40 2 jc code addr 41 2 ajmp code addr 42 2 orl data addr., a 43 3 orl data addr, #data 44 2 orl a, #data 45 2 orl a, data addr 46 1 orl a, @r0 47 1 orl a, @r1 48 1 orl a, r0 49 1 orl a, r1 4a 1 orl a, r2 4b 1 orl a, r3 4c 1 orl a, r4 4d 1 orl a, r5 4e 1 orl a, r6 4f 1 orl a, r7 50 2 jnc code addr 51 2 acall code addr 52 2 anl data addr, a 53 3 anl data addr, #data 54 2 anl a, #data 55 2 anl a, data addr 56 1 anl a, @r0 57 1 anl a, @r1 table 2?16: instruction opcodes in hexadecimal order hex code number of bytes mnemonic operands 58 1 anl a, r0 59 1 anl a, r1 5a 1 anl a, r2 5b 1 anl a, r3 5c 1 anl a, r4 5d 1 anl a, r5 5e 1 anl a, r6 5f 1 anl a, r7 60 2 jz code addr 61 2 ajmp code addr. 62 2 xrl data addr, a 63 3 xrl data addr, #data 64 2 xrl a, #data 65 2 xrl a, data addr 66 1 xrl a, @r0 67 1 xrl a, @r1 68 1 xrl a, r0 69 1 xrl a, r1 6a 1 xrl a, r2 6b 1 xrl a, r3 6c 1 xrl a, r4 6d 1 xrl a, r5 6e 1 xrl a, r6 6f 1 xrl a, r7 70 2 jnz code addr 71 2 acall code addr 72 2 orl c, bit addr 73 1 jmp @a + dptr 74 2 mov a, #data 75 3 mov data addr, #data table 2?16: instruction opcodes in hexadecimal order hex code number of bytes mnemonic operands .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 34 sept. 10, 2004; 6251-556-3ds micronas 76 2 mov @r0, #data 77 2 mov @r1, #data 78 2 mov r0, #data 79 2 mov r1, #data 7a 2 mov r2, #data 7b 2 mov r3, #data 7c 2 mov r4, #data 7d 2 mov r5, #data 7e 2 mov r6, #data 7f 2 mov r7, #data 80 2 sjmp code addr 81 2 ajmp code addr 82 2 anl c, bit addr 83 1 movc a, @a + pc 84 1 div ab 85 3 mov data addr, data addr 86 2 mov data addr, @r0 87 2 mov data addr, @r1 88 2 mov data addr, r0 89 2 mov data addr, r1 8a 2 mov data addr, r2 8b 2 mov data addr, r3 8c 2 mov data addr, r4 8d 2 mov data addr, r5 8e 2 mov data addr, r6 8f 2 mov data addr, r7 90 3 mov dptr, #data 16 91 2 acall code addr table 2?16: instruction opcodes in hexadecimal order hex code number of bytes mnemonic operands 92 2 mov bit addr, c 93 1 movc a, @a + dptr 94 2 subb a, #data 95 2 subb a, data addr 96 1 subb a, @r0 97 1 subb a, @r1 98 1 subb a, r0 99 1 subb a, r1 9a 1 subb a, r2 9b 1 subb a, r3 9c 1 subb a, r4 9d 1 subb a, r5 9e 1 subb a, r6 9f 1 subb a, r7 a0 2 orl c, /bit addr a1 2 ajmp code addr a2 2 mov c, bit addr a3 1 inc dptr a4 1 mul ab a5 ? reserved ? a6 2 mov @r0, data addr a7 2 mov @r1, data addr a8 2 mov r0, data addr a9 2 mov r1, data addr aa 2 mov r2, data addr ab 2 mov r3, data addr ac 2 mov r4, data addr ad 2 mov r5, data addr ae 2 mov r6, data addr af 2 mov r7, data addr table 2?16: instruction opcodes in hexadecimal order hex code number of bytes mnemonic operands .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 35 b0 2 anl c, /bit addr b1 2 acall code addr b2 2 cpl bit addr b3 1 cpl c b4 3 cjne a, #data, code addr b5 3 cjne a, data addr, code addr b6 3 cjne @r0, #data, code addr b7 3 cjne @r1, #data, code addr b8 3 cjne r0, #data, code addr b9 3 cjne r1, #data, code addr ba 3 cjne r2, #data, code addr bb 3 cjne r3, #data, code addr bc 3 cjne r4, #data, code addr bd 3 cjne r5, #data, code addr be 3 cjne r6, #data, code addr bf 3 cjne r7, #data, code addr c0 2 push data addr c1 2 ajmp code addr c2 2 clr bit addr c3 1 clr c c4 1 swap a c5 2 xch a, data addr c6 1 xch a, @r0 c7 1 xch a, @r1 table 2?16: instruction opcodes in hexadecimal order hex code number of bytes mnemonic operands c8 1 xch a, r0 c9 1 xch a, r1 ca 1 xch a, r2 cb 1 xch a, r3 cc 1 xch a, r4 cd 1 xch a, r5 ce 1 xch a, r6 cf 1 xch a, r7 d0 2 pop data addr d1 2 acall code addr d2 2 setb bit addr d3 1 setb c d4 1 da a d5 3 djnz data addr, code addr d6 ? not appli- cable ? d7 ? not appli- cable ? d8 2 djnz r0, code addr d9 2 djnz r1, code addr da 2 djnz r2, code addr db 2 djnz r3, code addr dc 2 djnz r4, code addr dd 2 djnz r5, code addr de 2 djnz r6, code addr df 2 djnz r7, code addr e0 1 movx a, @dptr e1 2 ajmp code addr e2 ? not appli- cable ? e3 ? not appli- cable ? table 2?16: instruction opcodes in hexadecimal order hex code number of bytes mnemonic operands .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 36 sept. 10, 2004; 6251-556-3ds micronas e4 1 clr a e5 2 mov a, data addr e6 1 mov a, @r0 e7 1 mov a, @r1 e8 1 mov a, r0 e9 1 mov a, r1 ea 1 mov a, r2 eb 1 mov a, r3 ec 1 mov a, r4 ed 1 mov a, r5 ee 1 mov a, r6 ef 1 mov a, r7 f0 1 movx @dptr, a f1 2 acall code addr f2 ? not appli- cable ? f3 ? not appli- cable ? f4 1 cpl a f5 2 mov data addr, a f6 1 mov @r0, a f7 1 mov @r1, a f8 1 mov r0, a f9 1 mov r1, a fa 1 mov r2, a fb 1 mov r3, a fc 1 mov r4, a fd 1 mov r5, a fe 1 mov r6, a ff 1 mov r7, a table 2?16: instruction opcodes in hexadecimal order hex code number of bytes mnemonic operands .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 37 2.3. interrupt 2.3.1. interrupt system external events and the real -time operation of on-chip peripherals require cpu serv ice asynchronous to the execution of any particular section of code. to couple the asynchronous activities of these functions to nor- mal program execution, a sophisticated multiple- source, four-priority-level, nested interrupt system is provided. 2.3.2. interrupt sources the tvt microcontroller core is capable of handling up to 24 interrupt sources. in type 17 interrupts are implemented. the rest are reserved for future use. the microcontroller acknowledges interrupt requests from these 17 sources. two external sources via the int0 and int1 pins and two additional external interrupts intx0 (p3.1) and intx1 (p3.7) are pro- vided. on-chip peripherals also use interrupts: one from each of the two internal counters, one from the analog digital converter and one from uart. in addi- tion there are four data acquisition related interrupts, two display related interrupts and one interrupt indicat- ing change of channel, two interrupts are generated by the wdt and pwm overflow in timer mode. timer 0 and timer 1 overflows are indicated by tcon(tf0) and tcon.(tf1). interrupts are gener- ated following a rollover in their respective registers (except in mode 3 when tcon(th0) controls the timer 1 interrupt). the external interrupts int0 and int1 are either level or edge triggered depending on bits in tcon and ircon . other external interrupts are level sensitive and active high. any edge triggering will need to be taken care of by individual peripherals. intx0 and intx1 can be programed to be either neg- ative or positive edge triggered. the analog digital converter interrupt is generated on completion of the analog digital conversion. 2.3.3. overview a simple overview of the interrupt handling is shown in fig. 2?4. . fig. 2?4: interrupt handling overview interrrupt request ien0.x highest priority level interrrupt request ien1.x interrrupt request ien2.x interrrupt request ien3.x eal ip1.x ip0.x ien0. 7 note: x = 0 to 5 lowest priority level p o l l i n g s e q u e n c e .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 38 sept. 10, 2004; 6251-556-3ds micronas 2.3.4. enabling interrupts interrupts are enabled through a set of interrupt enable registers ( ien0 , ien1 , ien2 , ien3 ). bits 0 to 5 of the interrupt enable registers each indi- vidually enable/disable a particular interrupt source. overall control is provided by bit 7 of ien0 (eal). when eal is set to ?0?, a ll interrupts are disabled: when eal is set to ?1?, interrupts are individually enabled or disabled through the other bits of the inter- rupt enable registers. eal may however be overrid- den by the disint signal which provides a global dis- able signal for the interrupt controller. 2.3.4.1. interrupt enable registers (ien0, ien1, ien2, ien3) the microcontroller has 4 interrupt enable registers. for each bit in these registers, a ?1? enables the corre- sponding interrupt and a ?0? disables it.see table 2? 17. 2.3.5. interrupt source registers all the interrupts except for timer0, timer1, external interrupt0, external interrupt1, external extra interrupt0 and external extra interrupt1 are generated by the respective blocks and are positive edge triggered. they are sampled in a central interrupt source register, the corresponding bit must be cleared by the software after entering the interrupt service routine. table 2?17: interrupt enable registers register name bit name 7 6 5 4 3 2 1 0 ien0 eal reserved ead eu et1 ex1 et0 ex0 ien1 edv eav exx1 ewt exx0 ex6 ien2 edh eah ecc epw ex13 ex12 ien3 eadw e24 ex21 ex20 ex19 ex18 see section 3. on page 110 for detailed register description. table 2?18: interrupt source registers register name bit name 7 6 5 4 3 2 1 0 cisr0 bit addressable l24 adc wtmr avs dvs pwtmr ahs dhs cisr1 it addressable cc adw iex1 iex0 see section 3. on page 110 for detailed register description. .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 39 2.3.6. interrupt priority for the purposes of assigning priority, the 24 possible interrupt sources are divided into groups determined by their bit position in the interrupt enable registers. their respective requests are scanned in the order as shown in table 2?19. each interrupt group may individually be assigned to one of four priority levels by writing to the ip0 and ip1 interrupt priority registers at the corresponding bit position. an interrupt service routine may only be interrupted by an interrupt of higher priority level. if two interrupts of different priority occur at the same time, the higher level interrupt will be serviced first. an interrupt cannot be interrupted by another interrupt of the same or a lower priority level. if two interrupts of the same priority level occur simul- taneously, the order in which the interrupts are ser- viced is determined by the scan order shown below. 2.3.6.1. interrupt priority registers (ip0 ip1) table 2?19: interrupt priority interrupt group interrupts in group high priority group priority 0external interrupt 0 external interrupt 6 1) external interrupt 12 1) external interrupt 18 1) high priority 1 timer 0 externalx interrupt 0 external interrupt 13 1) external interrupt 19 1) 2external interrupt 1 wt timer pw timer external interrupt 20 1) 3 timer 1 externalx interrupt 1 channel change external interrupt 21 1) 4 uart acquisition v-sync acquisition h-sync line 24 start 5 a to d display v-sync display h-sync a to d wake up 1) not implemented table 2?20: related registers register name bit name 7 6 5 4 3 2 1 0 ip0 bit addressable g5p0 g4p0 g3p0 g2p0 g1p0 g0p0 ip1 g5p1 g4p1 g3p1 g2p1 g1p1 g0p1 see section 3. on page 110 for detailed register description. .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 40 sept. 10, 2004; 6251-556-3ds micronas 2.3.7. interrupt vectors when an interrupt is served, a long call instruction is executed to one of the locations listed in table 2?21. table 2?21: interrupt vectors interrupt sources interrupt enable vector address (hex) interrupt request flag register bit external interrupt 0 ien0 ex0 0003 ie0 (tcon.1) timer 0 overflow ien0 et0 000b tf0 (tcon.5) external interrupt 1 ien0 ex1 0013 ie1 (tcon.3) timer 1 overflow ien0 et1 001b tf1 (tcon.7) uart ien0 eu 0023 r1(sco n.0) and t1(scon.1) a to d ien0 ead 002b adc(cisr0.6) external interrupt 6 ien1 ex6 0033 reserved externalx interrupt 0 ien1 exx0 003b cisr1(iex0) watchdog in timer ien1 ewt 0043 wtmr(cisr0.5) externalx interrupt 1 ien1 exx1 004b cisr1(iex1) acquisition v-sync ie n1 eav 0053 avs(cisr0.4) display v-sync ien1 edv 005b dvs(cisr0.3) external interrupt 12 ien2 ex12 0063 reserved external interrupt 13 ien2 ex13 006b reserved pwm in timer mode ien2 epw 0083 pwtmr(cisr0.2) channel change ien2 ecc 008b cc(cisr1.7) acquisition h-sync ien2 eah 0093 ahs(cisr0.1) display h-sync ien2 edh 009b dhs(cisr0.0) external interrupt 18 ien3 ex18 00a3 reserved external interrupt 19 ien3 ex19 00ab reserved external interrupt 20 ien3 ex20 00b3 reserved external interrupt 21 ien3 ex21 00bb reserved line 24 start ien3 e24 00c3 l24(cisr0.7) a to d wake up ien3 eadw 00cb adw(cisr1.6) .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 41 2.3.8. interrupt and memory extension when an interrupt occurs, the memory management unit (mmu) carries out the following sequence of actions: 1. the mex1 register bits are made available on sdatao[7:0]. 2. the mexsp register bits are made available on sadd[7:0]. 3. the stack read and write signals are set for a write operation. 4. a write is performed to external memory. 5. the mexsp stack pointer is incremented. 6. the interrupt bank bits ib19 - ib16 (mex2.3 - mex2.0) are copied to both the nb19 - nb16 and the cb19 - cb16 bits in the mex1 . then on return from the interrupt service routine: 1. the mexsp stack pointer is decremented. 2. the mexsp register bits are made available on sadd [7:0]. 3. the stack read and write signals are set for a read operation. 4. a read is performed on external memory. 5. sdatai [7:0] is copied to the mex1 register. this action allows the user to place interrupt service routines on specific banks. 2.3.9. interrupt handling external interrupt0, external interrupt1, timer0, timer1 and uart interrupt are handled as follows: ? interrupts are sampled at step5 phase2 in each machine cycle and the sampled interrupt informa- tion is polled during the following machine cycle. if an interrupt is active when it is sampled, it will be serviced provided: ? an interrupt of an equal or higher priority is not cur- rently being serviced. ? the polling cycle is not the final cycle of a multi- cycle instruction, and ? the current instruction is neither a reti nor a write either to one of interrupt enable registers or to one of the interrupt priority registers. note: active interrupts are only stored for one machine cycle. as a result, if an interrupt was active for one or more polling cycles but not ser- viced for one of the reasons given above, the interrupt will not be processed. for all other interrupts the interrupt request is stored as an interrupt flag in registers cisr0 and cisr1 . these request bits must be cleared by user software while servicing the interrupt. the interrupts always get serviced once raised regardless of the number of poll- ing cycles required to service them. 2.3.10. interrupt latency the response time in a single interrupt system is between 3 and 9 machine cycles. 2.3.11. interrupt flag clear in case of external interrupt0 and external interrupt1, if the external interrupts are edge triggered, the interrupt flag is cleared when entering into the interrupt service routine but if they are leve l triggered, the flag follows the signal applied to the port pin. timer/counter flags are cleared when entering into the interrupt service routine. all other interrupt flags, including iex0 and iex1 are not cleared by hardware. they must be cleared by software. 2.3.12. interrupt return for the proper operation of the interrupt controller it is necessary that all interrupt routines end with a reti instruction. .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 42 sept. 10, 2004; 6251-556-3ds micronas 2.3.13. interrupt nesting the process whereby a higher-level interrupt request interrupts a lower-level interrupt service routine is called ?nesting?. in this case the address of the next instruction in the lower-priority service routine is pushed onto the stack, the stack pointer is incremented by two and the micro- controller will continue the sw program execution from the memory location of the first instruction of the higher-level service routine. the last instruction of the higher-priority interrupt service program must be a reti-instruction. this instruction clears the higher ?pri- ority-level-active? flip-f lop. the reti command also makes that the microcontroller executes the next instruction of the lower-level interrupt service routine. since the lower ?priority-level-active? flip-flop has remained set, higher priority interrupts are re-enabled while further lower-priority interrupts remain disabled. 2.3.14. external interrupts the external interrupt request inputs (int0 and int1 ) can be programmed for either transition- activated or level-activated operation. control of the external inter- rupts is provided in the tcon register. table 2?22: related register register name bit name 7 6 5 4 3 2 1 0 tcon tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 see section 3. on page 110 for detailed register description. .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 43 2.3.15. extension of standard 8051 interrupt logic for more flexibility, sda 55xx family provides a new feature for the status detection of external extra inter- rupts ex0 and ex1 in an edge-triggered mode. now there is the possibility to tr igger an interrupt on the fall- ing and/or rising edge at the dedicated port 3 pin. in order to use this feature respective it0 and it1 bits in the tcon register must be set to activate edge trigger- ing mode. table 2?23 shows combination for interrupt0, however description is also true for interrupt1. note: if both exxxr and exxxf are set then both ris- ing and falling edges would generate an inter- rupt. minimum delay between the interrupts should be ensured by the software. if both the exxxr and exxxf are reset to 0, interrupt is disabled. external extra interrupts ex1 and ex2 are edge triggered interrupts only. table 2?23: interrupt combinations it0 ex0r ex0f interrupt 0 0 0 disabled 00 1 low level 0 1 0 high level 0 1 1 disabled 1 0 0 disabled 1 0 1 negative edge triggered 1 1 0 positive edge triggered 1 1 1 positive and negative edge triggered table 2?24: related register register name bit name 7 6 5 4 3 2 1 0 ircon exx1r exx1f exx0r exx0f ex1r ex1f ex0r ex0f see section 3. on page 110 for detailed register description. .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 44 sept. 10, 2004; 6251-556-3ds micronas 2.3.16. interrupt task function the microcontroller records the active priority level(s) by setting internal flip-flop( s). each interrupt level has its own flip-flop. the flip-flo p corresponding to the inter- rupt level being serviced is reset when the microcon- troller executes a reti-instruction. the sequence of events for an interrupt is: ? a source provokes an interrupt by setting its associ- ated interrupt request bit to let the microcontroller know an interrupt condition has occurred. ? the interrupt request is conditioned by bits in the interrupt enable and interrupt priority registers. ? the microcontroller acknowledges the interrupt by setting one of the four inte rnal ?priority-level active? flip-flops and performing a hardware subroutine call. this call pushes the pc (but not the psw ) onto the stack and, for some sources, clears the interrupt request flag. ? the service program is executed. ? control is returned to the main program when the reti-instruction is executed. the reti- instruction also clears one of the internal ?priority-level active? flip-flops. the interrupt request flags ie0, ie1, tf0 and tf1 are cleared when the microcontroller transfers control to the first instruction of the interrupt service program. 2.3.17. power saving modes the controller provides four modes in which power consumption can be significantly reduced. ? idle mode: the cpu is gat ed off from the oscillator. all peripherals except wdt (in watch dog mode) are still provided with the clock and are able to work. ? power-down mode: operation of the controller is turned off. this mode is used to save the contents of internal ram with a very low standby current. ? power-save mode: in this mode display generator, slicer_acq_sync, vadc, cadc, adc_wakeup, pwm, crt, wdt, dac, pll, and display (display, pixel clock and d sync) can be turned off. ? slow-down mode: in this mode the system fre- quency is reduced by one fourth. all modes are entered by software. special function register is used to enter one of these modes. 2.3.18. power-save mode registers. the table 3-25 lists the respective registers which con- trol or reflect the power-save modes. a description is given below. table 2?25: related registers register name bit name 7 6 5 4 3 2 1 0 psave cadc wakup sli_acq disp peri psavex bit addressable clk_src pll_res plls pcon smod pds idls sd gf1 gf0 pde idle see section 3. on page 110 for detailed register description. .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 45 2.3.19. idle mode entering the idle mode is done by two consecutive instructions immediately following each other. the first instruction has to set bit idle (pcon.0) and must not set bit idls (pcon.5). the following instruction has to set bit idls (pcon.5) and must not set bit idle (pcon.0). bits idle and idls will automatically be cleared after having been set. this double-instruction sequence is implemented to minimize the chance of unintentionally entering the idle mode. the following instruction sequence may serve as an example: orl pcon,#00000001 b ;set bit idle, bit idls must not be set. orl pcon,#00100000 b ;set bit idls, bit idle must not be set. the instruction that sets bit idls is the last instruction executed before going into idle mode. concurrent setting of the enable and the start bits does not set the device into the respective power sav- ing mode. the idle mode can be terminated by activation of any enabled interrupt (or a hardware reset). the cpu- operation is resumed, the interrupt will be serviced and the next instruction to be executed after reti-instruc- tion will be the one following t he instruction that set the bit idls. the port state and the contents of sfrs are held during idle mode. entering idle mode disables, vadc, acquisition, slicer, display, cadc and dac. however note that cadc wake up unit is still operational. leaving idle mode brings them to their original power save configuration (see section 2.3.21.). 2.3.20. power-down mode entering the power-down mode is done by two consec- utive instructions immediately following each other. the first instruction has to set bit pde (pcon.1) and must not set bit pds (pcon.6). the following instruc- tion has to set bit pds (pcon.6) and must not set bit pde (pcon.1). bits pde and pds will automatically be cleared after having been set. this double-instruction sequence is implemented to minimize the chance of unintentionally entering the power-down mode. the following instruction sequence may serve as an example: orl pcon,#00000010 b ;set bit pde, bit pds must not be set. orl pcon,#01000000 b ;set bit pds, bit pde must not be set. the instruction that sets bit pds is the last instruction executed before going into power-down mode. concurrent setting of the enable and the start bits does not set the device into the respective power sav- ing mode. if idle mode and power-down mode are invoked simul- taneously, the power-down mode takes precedence. the only exit from power-down mode is a hardware reset. the reset will redefi ne all sfrs, but will not change the contents of internal ram. 2.3.21. power-save mode bits in the psave register individually enable and dis- able different major blocks in the ic. note that power-save mode is independent of idle and power-down mode. in case of idle mode, blocks which are in power save mode remain in power-save mode. entering the power down mode with power-save mode is possible. however leaving the power down mode (reset) would initialize all th e power save register bits. note that power-save mode has a higher priority then idle mode. 2.3.22. slow-down mode sd bit in pcon register when sets divides the system frequency by 4. during the normal operation tvt pro is running with 33.33 mhz and in sd mode tvt pro runs with 8.33 mhz. in slow-down mode the slicer, acquisition and display are disabled regardless of power-save mode or other modes. all the pending request to the bus by these blocks are masked off. leaving slow-down mode restores the original status of these blocks. .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 46 sept. 10, 2004; 6251-556-3ds micronas 2.4. reset 2.4.1. reset sources tvtext pro can be reset by two sources: 1. externally by pulling down the reset pin rst . 2. internally by watch dog timer reset. please note that both reset signals use the same sig- nal path however a watchdog reset does not reset the clock pll. 2.4.2. reset filtering the rst pin uses a filter with a delay element, which suppresses jitter and spikes in the range of 25 ns to 75 ns. 2.4.3. reset duration with the active edge of the rst an internal signal resets all the flip flops asynchronously. the internal signal is released synchronously to the internal clock when it is stable as described below. the minimum duration of the external reset signal depends on the time required for the sda55xx internal crystal oscillator to reach it?s full amplitude swing and is dependent on the crystal used. during the period when the rst pin is held low, the pll is initialized and it gets locked. the high going reset pulse then initiates a sequence which requires one machine cycle (12 clock cycles) to initialize the microcontroller and all other registers and peripherals. 2.4.4. registers upon reset, all the registers are initialized to the values as defined in section 3. on page 110. 2.4.5. functional blocks after reset all the functional blocks will be in a defined known state. microcontroller, acquisition and display will not have any pending bus requests after reset. 2.4.6. rams the hw reset and its related logic does not initialize any rams. 2.4.7. analog blocks after the power up reset the dac will output a fixed value. adc and the adc wake up unit do not generate any interrupts till the 12 c ycle long reset sequence is completed. 2.4.8. microcontroller after the reset sequence the program counter initial- izes to 0000 h and starts execution from this location in the rom. location 0000h to 0002h are reserved for the a jump instruction to the initialization routine. 2.4.9. ports with the reset all ports are set in to the input mode. exception are port 4.0, 4.1 and 4.4, which by default after reset are assigned as data outputs for the address lines a17, a18, a19. 2.4.10. initialization phase 2.4.10.1. acquisition after the reset the acquis ition will not generate any memory accesses to the ram, due to the fact that the acq_start bit is initialized to ?0?. the microcontroller should then initialize th e vbi buffer and set the acq_start bit (by software). the acquisition will not generate any accesses to the ram if the h / v syn- chronization is not achieved. 2.4.10.2. display after reset the dacs will output a fix value as defined by en_dgout, which is reset to ?0?. cor_bl is reset to a level indicating cor = ?0? and blank = ?1?. the microcontroller should initialize the display mem- ory and set the en_dgout (ocd_ctrl) bit. .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 47 2.5. memory organization the microcontroller has separate program and data memory spaces. memory spaces can be further clas- sified as: ? program memory ? internal data memory of 256 bytes (cpu ram) ? internal extended data memory (xram) a 16-bit program counter and a dedicated banking logic provide the microcontroller with 1 mbyte address- ing capability (with the ro m-less versions, up to 20 address lines are available). the program counter allows the user to execute calls and branches to any location within the program mem- ory space. data pointers allow to move data to and from extended data ram. there are no instructions that permit program execu- tion to move from the program memory space to any data memory space. 2.5.1. program memory program rom consists of 128 kbyte on chip rom for mask programmed versions. locations ?0000? through ?0002? are reserved for the long jump instruction to the initialization routine. fol- lowing reset, the cpu always begins execution at loca- tion ?0000?. locations ?0003? through ?00cb? are can be reserved for the interrupt-request service routines if required. table 2?26: program memory interrupt source vector address external interrupt 0 0003 timer 0 overflow 000b external interrupt 1 0013 timer 1 overflow 001b uart 0023 adc 002b reserved 0033 externalx interrupt 0 003b watchdog timer 0043 external x interrupt 1 004b acquisition v sync 0053 display v sync 005b reserved 0063 reserved 006b reserved 0073 reserved 007b pwm in timer mode 0083 channel change 008b acq h sync 0093 display h sync 009b reserved 00a3 reserved 00ab reserved 00b3 reserved 00bb line 24 start 00c3 a to d wake up 00cb .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 48 sept. 10, 2004; 6251-556-3ds micronas 2.5.2. internal data ram internal data ram is sp lit into cpu ram and xram 2.5.2.1. cpu ram 2.5.2.1.1. address space the internal cpu ram (iram) occupies address space 00 h to ff h . this space is further split into two regions. the lower 128 bytes (00 h -7f h ) can be accessed using both direct and indirect register addressing method. the upper half of 128 bytes (80 h -ff h ) can be accessed using the ?register indirect method? only. register direct method for this address space (80 h - ff h ) is reserved for special function register access. 2.5.2.1.2. registers controller registers are also located in iram. four banks of eight registers each occupy locations 0 through 31. only one of these banks may be enabled at a time through a two-bit field in the psw . 2.5.2.1.3. bit addressable ram area 128-bit locations of the on-chip ram are accessible through direct addressing.these bits reside in internal data ram at byte locations 32 through 47. 2.5.2.1.4. stack the stack can be located anywhere in the internal data ram address space. the stack depth is limited only by the available internal data ram, thanks to an 8-bit re- locatable stack pointer. the stack is used for storing the program counter during subroutine calls and may also be used for passing parameters. any byte of inter- nal data ram or special function registers accessible through direct addressing can be pushed/popped. by default stack pointer always has a reset value of 07 h . 2.5.2.2. extended data ram (xram) an additional on-chip ram space called ?xram? extends the capacity of the internal ram. up to 16 kilobytes of xram are accessed by movx @dptr. the xram is located in the upper area of the 64k address space. 1 kbyte of the xram, called vbi buffer, is reserved for storing teletext data. 1 kbyte of address space can be allocated as cpu work space. three kilobyte of ram are reserved as display ram. the rest of the ram can be configured either as teletext page memory or drcs (dynamically redefina ble character set) mem- ory. 2.5.2.2.1. extended data memory address map- ping the xram is mapped in the address space from c000 h to ffff h . 16 kbytes are implemented as on- chip memory. the address space of the 16k block is decoded starting from c000 h . note that this decoding is done independent of the memory banking. that means that in all 16 available banks of 64k, the upper 16kbyte long address space is reserved for internal extended data memory. this decoding method has the advantage, that when copying data back and forth between on-chip ram and off-chip ram, there is no need to switch the memory banks. .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 49 2.5.3. memory extension the controller provides four additional address lines a16, a17, a18 and a19. these additional address lines are used to access program and data memory space of up to 1mbyte. the extended memory space is split into 16 banks of 64 kbyte each. a16 is available as a dedicated pin, a17, a18 and a19 however work as alternate f unction to port pins p4.0, p4.1 and p4.4 respectively. refer to register cscr1 (a19 _p4_4, a18 _p4_1,a17 _p4_0). the functionality for memory extension is provided by a memory management un it (mmu) which includes the four sfr registers mex1 , mex2 , mex3 and mexsp . 2.5.3.1. memory extension registers the following registers are present in the memory management unit. these registers can be read and written through mov instructions like any other sfr register. except for the cb bits in mex1 - which are read only - and can be written only by the mmu. during normal operation user must not write to the mexsp register . 2.5.3.2. reset value in order to insure proper 8051 functionality all the bits in sfr mex1 , mex2 , mex3 and mexsp are initial- ized to ?0? . table 2?27: related registers register name bit name 7 6 5 4 3 2 1 0 mex1 cb[19:16] nb[19:16] mex2 mm mb[18:16] ib[19:16) mex3 mb19 ub3 ub4 mx19 mxm mx[18:16] mexsp reserved sp[6:0] see section 3. on page 110 for detailed register description. .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 50 sept. 10, 2004; 6251-556-3ds micronas 2.5.4. instructions on which memory extension would act the following instruction are used to access the extended memory space: ? ljmp ?movc ?movx ?lcall ?acall ?ret ?reti 2.5.4.1. program memory banking (ljmp) after reset the bits for current bank (cb) and next bank (nb) are set to zero. this insures that the microcontrol- ler starts like a standard 8051 microcontroller at address 00000 h . when a jump to another bank is required, software changes the bits nb16 ? 19 to the appropriate bank address (before ljmp instruction). when a ljmp is encountered in the code, the mmu copies the nb16 ? 19 (next bank) bits to cb16 ? 19 (current bank). note that the nb bits are not destroyed. bits related the extended memory address would appear at the pins a16 ? a19. these address line have the same timing requirements compared to nor- mal address lines a0?a15 and must be stable at the same time. only with ljmp above mentioned action is performed, other jmp instructions have no effect. cb bits are read only. 2.5.4.2. movc handling there are two modes for movc instructions. the mode is selected by mm bit in mex2 . 2.5.4.2.1. movc with current bank when mm bit = ?0?, movc will access the current bank. the cb16 ? cb19 bits would appear as addresses a16 ? a19 during movc instructions. 2.5.4.2.2. movc with memory bank when mm bit = ?1?, movc will access the memory bank. the mb16 ? mb19 bits would appear as addresses a16 ? a19 during movc instructions. note: mex1 is not destroyed. 2.5.4.2.3. movx handling there are two modes for movx instructions. the mode is selected by mxm bit in mex3 . 2.5.4.2.4. movx with current bank when mxm bit = ?0?, movx will access the current bank. the cb16 ? cb19 bits would appear as addresses a16 ? a19 during movx instructions. 2.5.4.2.5. movx with data memory bank when mxm bit = ?1?, movx will access the data mem- ory bank. the mx16 ? mx19 bits would appear as address a16 ? a19 during movx instructions. note: mex1 is not destroyed. 2.5.4.3. calls and interrupts 2.5.4.3.1. memory extension stack for interrupts and calls the memory extension stack is required. stack pointer mexsp provides the stack depth of up to 128 bytes. stack width is 1 byte. in tvtpro 128 bytes stack is implemented. 2.5.4.4. stack full no indication for stack full is provided. the user is responsible to read mexsp sfr to determine the sta- tus of the mexsp stack. 2.5.4.5. timing the mmu outputs the address bits a19 ? a16 at the same time as the normal addresses a15 ? a0. stack operation signals, sadd[6:0], sdatai[7:0], sdatao[7:0], srd and swr have the same timing as internal ram signals. 2.5.4.6. interfacing extended memory the address bits a19, a18, a17, a16 are used to decode extended memory. 2.5.4.7. application examples movc .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 51 fig. 2?5: pc and dptr on different banks 2.5.4.7.1. sample code fig. 2?6 shows an assembler program run, performing the following actions: 1. start at bank 0 at 00000. 2. set isr-page to bank 2. 3. jump to bank 1 at address 25. 4. being interrupted to bank 2 isr. 5. call a subprogram at bank 2 address 43. 6. after return read data from bank 2. 2.5.4.8. rom and romless version the xrom pin determines whether the on-chip or the off-chip rom is accessed. if no internal rom is to be used, then the xrom pin (in romless version) should be driven ?low?. the con- troller then accesses the ex ternal rom only. in the rom version this pin is internally pulled high, indicat- ing that no external rom is available. fig. 2?6: program code 2.6. uart the serial port is full duplex, meaning it can transmit and receive simultaneously. it is also receive-buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the receive register (however, if the first byte still hasn?t been read by the time the reception of the second byte is complete, one of the byte s will be lost). the serial port receive and transmit registers are both accessed at special function register sbuf . writing to sbuf loads the transmit register, and reading sbuf accesses a physically sepa rate receive register. the frequencies and baud rates depend on the inter- nal system clock used by the serial interface. 2.6.1. operation modes of the uart the serial port can operate in 4 different modes. in all four modes, transmission is initiated by any instruction that uses sbuf as a destination register. reception is initiated in mode 0 by the condition rl = 0 and ren = 1. reception is initia ted in the other modes by the incoming start bit if ren = 1. 2.6.1.1. mode 0 serial data enter and exit through pin rxd (p3.7). txd (p3.1) outputs the shift clock. 2.6.1.2. mode 1 10 bits are transmitted (through txd) or received (through rxd): a start bit (0), 8 data bits (lsb first), and a stop bit (1). on reception, the stop bit goes into bit rb8 in special function register scon . the baud rate is variable. 2.6.1.3. mode 2 11 bits are transmitted (through txd) or received (through rxd): a start bit (0), 8 data bits (lsb first), a programmable 9 th data bit, and a stop bit (1). on trans- mission, the 9 th data bit (tb8 in scon ) can be assigned the value of 0 or 1. or, for example, the parity bit (p, in the psw ) could be moved into tb8. on recep- tion, the 9 th data bit goes into rb8 in the special func- tion register scon , while the stop bit is ignored. the baud rate is programmable via sfr-bit smod. .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 52 sept. 10, 2004; 6251-556-3ds micronas 2.6.1.4. mode 3 11 bits are transmitted (through txd) or received (through rxd): a start bit (0), 8 data bits (lsb first), a programmable 9 th data bit and a stop bit (1). in fact, mode 3 is the same as mode 2 in all respects except the baud rate. the baud rate in mode 3 is variable. 2.6.2. multiprocessor communication modes 2 and 3 of the serial interface of the controller have a special provision fo r multiprocessor communi- cation. in these two modes, 9 data bits are received. the 9th bit goes into register scon bit rb8. then comes a stop bit. the port can be programmed such that when the stop bit is received, the serial port inter- rupt will be activated only if rb8 = 1. this feature is enabled by setting bit sm2 in scon . a way to use this feature in multip rocessor communications is as fol- lows: when the master microcontroller wants to transmit a block of data to one of the several slaves, it first sends out an address byte which identifies the target slave. in an address byte the 9th bit is a ?1?, a data byte is identified with a ?0? as 9th. bit. if the scon register bit sm2 i s set to ?1?, no slave will be interrupted by a data byte. an address byte how- ever, will interrupt all slaves, so that each slave can examine the received byte and see if it is being addressed. the addressed slave will clear its sm2 bit and prepare to receive th e data bytes that will be transmitted by the master. the slaves that were not addressed leave their sm2 bits set to 1 and go on with the execution of the currently running program and ignore the data byte transmission on the bus. the bit sm2 has no effect in mode 0, and in mode 1 the sm2 bit can be used to check the validity of the stop bit. in a mode 1 reception, if sm2 = 1, the receive inter- rupt will not be activated unless a valid stop bit is received. table 2?28: select mode 0-3 for uart sm0 sm1 mode description baud rate (cdc = 0) 000 shift reg.f system/12 0 1 1 8-bit uart variable 1 0 2 9-bit uart f system/64 , f system/32 1 1 3 9-bit uart variable table 2?29: related register register name bit name 7 6 5 4 3 2 1 0 scon sm0 sm1 sm2 ren tb8 rb8 ti ri see section 3. on page 110 for detailed register description. .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 53 2.7. general purpose timers/counters two independent general purpose 16-bit timer/ counters are integrated for use to measure time inter- vals, pulse widths, counting events, and causing peri- odic (repetitive) interrupts. both can be configured to operate as timer or event counter. in the ?timer? function, the registers tlx and/or thx (x = 0, 1) are incremented once every machine cycle. as one machine cycle has a length of 12 cycles of the oscillator the counting frequency is fcrystal /12. in the ?counter? function, the registers tlx and/or thx (x = 0, 1) are incremented in response to a 1-to-0 tran- sition at its corresponding external input pin, t0 or t1. in this function, the external input is sampled during every machine cycle. if the samples taken show a ?1? in one cycle and a ?0? in the next cycle, the count is incre- mented. the new count value appears in the register during the cycle following the one in which the transi- tion was detected. since it takes 2 machine cycles (24 oscillator periods) to reco gnize a ?1?-to-?0? transi- tion, the maximum count rate is 1/24 of the oscillator frequency. there are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it should be held for at least one full machine cycle. 2.7.1. timer/counter 0: mode selection timer/counter 0 can be configured in one of four oper- ating modes, which are selected by bit-pairs (m1, m0) in tmod register. see section 2.7.1. on page 53. 2.7.1.1. mode 0 putting timer/counter 0 into mode 0 makes it looks like an 8048 timer, which is an 8-bit counter with a divide- by-32 prescaler. table 2?32 shows the mode 0 opera- tion as it applies to timer 0. in this mode, the timer register is configured as a 13-bit register. as the count rolls over from all ?1? to all ?0?, it sets the timer interrupt flag tf0. the timer input is enabled if tr0 = 1 and either gate = 0 or int0 =1. (setting gate = 1 allows the timer to be controlled by external input int0 , to facilitate pulse width measure- ments.) tr0 is a control bit in the special function reg- ister tcon (see section 2.8.5. on page 57). gate is contained in register tmod (see section 2.7.4. on page 54). the 13-bit register consists of all 8 bits of th0 and the lower 5 bits of tl0 . the upper 3 bits of tl0 are not valid and should be ignored. setting the run flag tr0 does not clear the registers. 2.7.1.2. mode 1 mode 1 is the same as mode 0, except that all 16 bits of the timer/counter 0 register are being used. 2.7.1.3. mode 2 mode 2 configures the timer/counter 0 register as an 8-bit counter tl0 with automatic reload. the high byte tho is used as storage for the reload value. overflow from tl0 not only sets tf0, but also reloads tl0 with the contents of th0 , which is preset by software. the reload leaves th0 unchanged. 2.7.1.4. mode 3 timer/counter 0 in mode 3 establishes tl0 and th0 as two separate counters. tl0 uses the timer 0 control bits: c/t, gate, tr0, int0 and tf0. th0 is locked into a timer function (counting machine cycles) and takes over the use of tr1 and tf1 from timer 1. thus, th0 now controls the ?timer 1? interrupt. mode 3 is provided for applications requiring an extra 8-bit timer or counter. with timer 0 in mode 3, the microcontroller can operate as if it has three timers/ counters. when timer 0 is in mode 3, timer 1 can be turned on and off by switching it out of and into its own mode 3, or can still be us ed in any application not requiring an interrupt. 2.7.2. timer/counter 1: mode selection timer/counter 1 can also be configured in one of four modes, which are selected by its own bitpairs (m1, m0) in tmod register. the serial port receives a pulse each time that timer/ counter 1 overflows. this pulse rate is divided to gen- erate the transmission rate of the serial port. modes 0 and 1 are the same as for counter 0. 2.7.2.1. mode 2 the ?reload? mode is reserved to determine the fre- quency of the serial clock signal (not implemented). 2.7.2.2. mode 3 when counter 1's mode is reprogrammed to mode 3 (from mode 0, 1 or 2), it disables the increment counter. this mode is provided as an alternative to using the tr1 bit (in tcon register) to start and stop timer/counter 1. .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 54 sept. 10, 2004; 6251-556-3ds micronas 2.7.3. configuring th e timer/counter input the use of the timer/counter is determined by two 8-bit registers, tmod (timer mode) and tcon (timer con- trol). the input to the counter circuitry is from an exter- nal reference (for use as a counter), or from the on- chip oscillator (for use as a timer). the operation mode depends on whether tmod's c/t-bit is set or cleared, respectively. when used as a time base, the on-chip oscillator frequency is divid ed by twelve or six before being used as the counter input. when tmod's gate bit is set (1), the external reference input (t1, t0) or the oscillator input is gated to the counter conditional upon a second external input (int0 ) or (int1 ) being high. when the gate bit is zero (0), the external refer- ence, or oscillator input, is unconditionally enabled. in either case, the normal interrupt function of int0 and int1 is not affected by the counter's operation. if enabled, an interrupt will occu r when the input at int0 or int1 is low. the counters are enabled for incre- menting when tcon 's tr1 and tr0 bits are set. when the counters overflow, the tf1 and tf0 bits in tcon get set, and interrupt requests are generated. the counter circuitry counts up to all 1's and then over- flows to either 0's or the reload value. upon overflow, tf1 or tf0 is set. when an instruction changes the timer's mode or alters its control bits, the actual change occurs at the end of the instruction's execution. 2.7.4. timer/counter mode register table 2?30: tmod register name bit name 7 6 5 4 3 2 1 0 tmod gate c/tm1m0gatec/tm1m0 timer 1 timer 0 see section 3. on page 110 for detailed register description. table 2?31: tcon register name bit name 7 6 5 4 3 2 1 0 tcon tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 see section 3. on page 110 for detailed register description. .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 55 2.8. capture reload timer the capture control timer is a 16 bit up counter, with special features suited for easier infrared decoding by measuring the time interval between two successive trigger events. trigger events can be positive, negative or both edges of a digital input signal (port 3.2 or 3.3). a built in spike suppression unit (ssu) can be used for suppressing pulses with obviously too small or too long time duration at the beginning of an expected telegram, thereby relieving the fw of processing cor- rupted telegrams. this is especially useful in idle mode. 2.8.1. input clock the input clock is f cct and is same as the system clock frequency divided by two. in normal mode the system frequency is 33.33 mhz (f cct = 16.66 mhz) and in slow down mode (sd mode) it is 8.33 mhz (f cct = 4.16 mhz). pr prescaler bit: when set the input clock is further divided by 2, setting pr1 divides further by 8. if the operation is changed to the sd mode the fre- quency is adjusted accordingly so that maximum time resolution of 15.73 ms or 251.66 ms is achieved depending on prescaler pr bits. 2.8.2. reset values all the eight 8 bit registers crt_rell , crt_relh , crt_capl , crt_caph , crt_mincapl , crt_mincaph , crt_con0 and crt_con1 are reset to 00 h . 2.8.3. functional description 2.8.3.1. port pin either port p3.3 or p3.2 can be selected as capture input via sel bit. capture event can be programmed to occur on rising or falling edge or both using the bits rise and fall bits. 2.8.3.2. slow down mode sd bit when set, reduces the system frequency to 8.33 mhz. however the clk to the counter has a fix fre- quency (for a particular prescaler value). this is achieved by a divide by 4 chain, which divides the incoming frequency by 4 when sd = 0 and feeds the incoming signal directly to the counter when sd = 1. 2.8.3.3. run when the counter is started (run), a 16 bit reload value is automatically loaded into the 16 bit counter. (note: rel bit is irrelevant in case of run function). setting run bit resets the first and ov bit. all the control bits pr, plg, rel, run, rise, fall, sel, start, int_src, sd can be changed anytime dur- ing the operation. these changes take immediate effect. there is no protected mode when the counter is running. 2.8.3.4. overflow in case no capture event occurs, the counter keeps on counting till it overflows from ffff h to 0000 h. at this transition the ov bit is set. after the overflow the counter keeps on counting. overflow does not reload the reload value. note that the ov bit is set by the counter and can be reset by software. 2.8.3.5. modes there are three different modes in which the counter can be used. ? normal capture mode ? polling mode ? capture mode with spike suppression at the start of an ir telegram for each change in the mo de selection it is recom- mended to reset the run bit (if it is not already at 0), set the appropriate mode bit and then re-start the counter by setting the run bit again. for each of the capture modes the event is captured based on the crtcon0 (bit rise) and crtcon0 (bit fall). table 2?32: timer/counter mode selection mode start plg normal capture mode 0 0 capture mode with spike suppression 10 polling mode x 1 .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 56 sept. 10, 2004; 6251-556-3ds micronas 2.8.3.6. normal capture mode normal capture mode is started by setting the run bit (0 --> 1) and plg = 0, st art = 0. setting run bit will reload the counter with reload value and reset the overflow bit and counter will start to count. upon event on the selected port pin, contents of the counter are copied to the capture registers crt_caph and crt_capl . in capture mode if rel bit is set counter is automati- cally reloaded upon occurrence of the event with the reload value and starts to count. if however rel bit is not set then the counter continues to count from the current value. ov bit is not effected by the capture event. note: min_cap register has no functionality in this mode. interrupt would be generated from crt, how- ever it will only be registered in the int source register if intsrc bits in the cscr1 are appropri- ately set. it is not required to use the crt gen- erated interrupt in this mode. direct pin interrupt can be used. 2.8.3.7. polling mode the polling mode is started by setting the plg bit to ?1? (start bit is in don?t care for this mode). setting the run bit will reload the counter with the reload value and reset the overflow bit and start the counting. in the timer polling mode, th e capture register mirrors the current timer value, note that in this mode any event at the selected port pin is ignored. upon overflow the ov bit is set. note: interrupts are not generated as events are not recognized. 2.8.3.8. capture mode with spike suppression at the start of an infrared telegram this mode is specially b een implemented to prevent false interrupt from being generated specially in idle mode while waiting for a new infrared telegram. this mode is entered by setting the start bit (plg = 0). the software sets the start bit to indicate it is expecting a new telegram. setting the run bit will reload the counter with the reload value and reset the overflow bit and start the counting. 2.8.3.9. first event on occurrence of the capture event, the counter value is captured and the comparator then sets the first bit. the interrupt is suppressed. the ov bit is reset and the counter reloads the reload value (regardless of the status of rel bit) and starts counting again. 2.8.3.10. second event on occurrence of second capture event, the counter value is captured and the interrupt is triggered if the capture value exceeds the value in the min_cap regis- ter and the ov bit is not set. first bit is reset. the counter will now continue in the normal capture mode. software may reset the start bit if the capture value is detected as a valid pulse of an ir telegram. if the pulse was invalid then software must stop the counter and start again (run bit & first reset and then set) with start bit set to wait for a new telegram. if capture value is less then or equal to min_cap value or ov bit has been set, that is spike has been detected and interrupt is suppressed. ov bit would be reset counter would be reloaded with reload value (regard- less of rel bit). in this case if either rise or fall bit were set then counter will wait for the se cond event (first = 1), if rise and fall both were set then counter will wait for the first event (first = 0). 2.8.3.11. capture reload timer crt interrupt the capture reload timer crt can generate an inter- rupt if the spice suppress ion unit ssu is employed. the crt unit uses the same interrupt line as int1 and int0 . the interrupt line is selected by the sel bit. note that when using crt to generate an interrupt, the direct interrupt source from port 3.2 or 3.3 (which ever is selected) should be switched to crt ( cscr1 (intsrc0), cscr1 (intsrc1)). if the application uses port pins directly to generate interrupts, then these bits should be reset. note that by default int1 and int0 are mapped to p3.3 and p3.2. the ssu generates an interrupt signal as a pulse, which is captured in the interrupt source register tcon (ie1 or ie0). while using this mode tcon (it0 or it1) must be set to 1 (edge triggered) and ircon (ex1r or ex0r) must be set to 1 and ircon (ex1f or ex0f) must be set to 0. for further information on interrupts please refer to section 2.3. on page 37. .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 57 2.8.3.12. counter stop the counter can be stopped any time by resetting the run bit. if the counter is stopped and started again (reset and set the run bit), the counter reloads with the reload value and reset the ov bit. 2.8.4. idle and power-down mode in idle mode the capture reload timer crt continues to function normally, unless it has been explicitly shut down via the psavex (peri) bit. in power down mode the capture reload timer crt is shut off. 2.8.5. registers the crt_rell and crt_relh are the reload registers (sfr address b7 h and b9 h ), crt_caph and crt_capl are the corresponding capture registers (sfr address ba h and bb h ). crt_mincapl and crt_mincaph (sfr address bc h , bd h ) are mini- mum capture registers. crt_con0 (e5 h ) and crt_con1 are the control registers. table 2?33: related registers register name bit name 7 6 5 4 3 2 1 0 crt_rell rell[7:0] crt_relh relh[7:0] crt_capl capl[7:0] crt_caph caph[7:0] crt_mincapl minl[7:0] crt_mincaph [7:0] crt_con0 ov pr plg rel run rise fall sel crt_con1 reserved reserved reserved reserved reserved pr1 first start see section 3. on page 110 for detailed register description. .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 58 sept. 10, 2004; 6251-556-3ds micronas fig. 2?7: block diagram table 2?34: time resolution sd f sys pr1 pr f ctr f ctr time res. max pulse width 0 33.33 mhz 00f sys /8 mhz 4.17 mhz 240 ns 15.73 ms 01f sys /16 mhz 2.083 mhz 480 ns 31.46 ms 10f sys /64 mhz .5208 mhz 1920 ns 125.83 ms 11f sys /128 mhz .2604 mhz 3840 ns 251.66 ms 18.33mhz 00f sys /8 mhz 4.17 mhz 240 ns 15.73 ms 01f sys /16 mhz 2.083 mhz 480 ns 31.46 ms 10f sys /64 mhz .5208 mhz 1920 ns 125.83 ms 11f sys /128 mhz .2604 mhz 3840 ns 251.66 ms p 3.3 p 3.2 fall sel rise fall rise 16 bit ctr reload capture fcct run 1 bit ctr pr 1 bit ctr div 2 compare min_cap first int spike supression unit start sd intsrc1 intsrc0 int0 int1 .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 59 2.9. pulse width modulation unit the pulse width modulation unit consists of 6 chan- nels with 8 bit resolution and 2 channels with 14 bit resolution pwm channels. pwm channels are pro- grammed via special function registers and each chan- nel can be enabled and disabled individually. 2.9.1. reset values all the pwm unit registers as there are: pwme, pwcomp8 0-5, pwcomp14 0-1, pwmcompext14 0-1, pwml and pwmh by default are reset to 00 h . 2.9.2. input clock the input clock fpwm to the pwm unit pwmu is derived from f sys . f sys is 33.33 mhz in normal mode and in slowdown mode 8.33 mhz. in normal mode f sys is divided by 2 and in slow down mode it is directly fed to the pwmu. therefore pwm unit is counting at 16.5 mhz in normal mode and 8.25 mhz in slow down mode. if the pr bit pcompext14 0 (bit 0) is set the then the counting frequency is half of that. in addition the pwm_direct bit makes it possible to run the pwm counter at system frequency, ignoring the pr bit and the built in divide by 2 prescaler. to reduce noise radiation, the different pwm-channels are not switched ?on? si multaneously with the same counter value. the channels are switching on with one clock cycle delay to the next channel: channel 0: 0 clock cycles delayed, channel 1: 1 clock cycle delayed, ?, channel 5: 5 clock cycles, ?, pwm14_0: 6 clock cycles, pwm14_1: 7 clock cycles delayed. 2.9.3. port pins port 1 is a dual function port. under normal mode it works as standard port 1, in the alternate function mode it outputs the pwm channels. p1.0 ? p1.5 corresponds to the six 8 bit resolution pwm channels pwm8_0 ? pwm8_5. p1.6 and p1.7 corresponds to the two 14 bit resolution pwm chan- nels pwm14_0 and pwm14_1. pwm channels can be individually enabled by corresponding bits in the pwme register provided the pwm_tmr bit is not set (timer mode start bit). 2.9.4. functional description 2.9.4.1. 8-bit pwm the base frequency of a 8 bit resolution da converter channel is derived from the overflow of a six bit counter. on every counter overflow, the enabled pwm lines would be set to 1. except in the case it the compare value is set to zero. in case the comparator bits (7 ? 2) are set to 1, the high time of the base cycle is 63 clock cycles. in case all the comparator bits (7 ? 0) including the stretching bits are set to 1, the high time of the full cycle (4 base cycles) is 255 clock cycles. the corresponding pwcomp8x register determines the duty cycle of the channel. if the counter value is equal to or greater than the compare value then the output channel is set to zero. the duty cycle can be adjusted in steps of fpwm as mentioned in table 2?36. in order to achieve the same resolution as 8-bit counter, the high time is stretched periodically by one clock cycle. the stretching cycle is determined based on the two least significant bits in the corresponding pwcomp8x register. the relationship for the stretching cycle can be seen in table 2?35 and the example below. fig. 2?8: 8-bit pwm and the stretching cycles table 2?35: 8-bit pwm stretching cycle relationship pwcomp8x cycle stretched bit 1 1, 3 bit 0 2 ? stretched ? cycle 1 cycle 2 cycle 3 cycle 0 .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 60 sept. 10, 2004; 6251-556-3ds micronas 2.9.4.2. 14-bit pwm the base frequency of a 14 bit resolution channel is derived from the overflow of a eight bit counter. on every counter overflow, the enabled pwm lines would be set to 1 - except in the case where the com- pare value is set to zero. the corresponding pwcomp14x register determines the duty cycle of the channel. when the counter value is equal to or greater than the compare value then the output channel is set to zero. the duty cycle can be adjusted in steps of fpwm as mentioned in table 2?36. in order to achieve the same resolution as 14bit counter, the high time is stretched periodically by one clock cycle. stretching cycle is determined based on the bit 7?1 in the corr esponding pwcompext14x register. 2.9.5. cycle time table 2?36: 14-bit pwm stretching cycle relationship pwcompext14x cycle stretched bit 7 1, 3, 5, 7, ?, 59, 61, 63 bit 6 2, 6, 10, ?, 54, 58, 62 bit 5 4, 12, 20, ?, 52, 60 bit 4 8, 24, 40, 56 bit 3 16, 48 bit 2 32 table 2?37: cycle time pwm resolution slow down (sd) pwm_ pr pwm_ direct f sys [mhz] counting rate [mhz] base cycle time [ s] full cycle time [ s] 8 bit 0 0 0 33.33 16.66 3.84 15.37 1 0 0 8.33 8.33 7.68 30.73 0 1 0 33.33 8.33 7.68 30.73 1 1 0 8.33 4.16 15.37 61.46 0 x 1 33.33 33.33 1.92 7.68 1 x 1 8.33 8.33 7.68 30.73 14 bit 0 0 0 33.33 16.66 15.37 983.4 1 0 0 8.33 8.33 30.7 1967 0 1 0 33.33 8.33 30.7 1967 1 1 0 8.33 4.16 61.4 3934 0 x 1 33.33 33.33 7.68 492 1 x 1 8.33 8.33 30.7 1967 .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 61 2.9.6. power-down, idle and power-save mode in idle mode the pulse width modulation unit pwmu continues to function normally, unless it has been explicitly shut down by psave (peri). note that in psave mode all channels are frozen and the pins are switched to port output mode making it possible to use the port lines. in power-down mode the pulse width modulation unit pwmu is shut off. 2.9.7. timer the pulse width modulation unit pwm unit uses a sin- gle 14 bit timer to generate signals for all 8 channels. the timer is mapped into the sfr address space and hence is readable by the controller. timer is enabled (running) if one of the pwm channels is enabled in pwme. if all the channels are disabled counter is stopped. enabling one of the channels will reset the timer to 0 and start. note that this reset is done for the first enabled channel. all other channels enabled later will drive the output from the current value of the counter. if all the channels are disabled then it can be used as a general purpose timer, by enabling it with pwm_tmr bit in pwch. setting pwm_tmr bit switches to timer mode and starts the timer. the timer always starts from a reset value of 0 (ov also reset to 0). timer can be stopped any time by turning off the pwm_tmr bit. if the timer overflows it sets an over flow bit ov (bit 6) pwch and interrupt bit cisr0 (pwtmr) in the central interrupt register. if the corresponding interrupt enable bit ien2(epw) is set the interrupt will be serviced. ov bit and pwtmr bits must be reset by the software. note: before utilizing the ti mer for pwm channels pwm_tmr bit must be reset. on reset the cisr0 (pwtmr) bit is initialized to 0, however if the counter overflows this bit might be set along with ov bit. however clearing ov bit does not clear the cisr0 (pwtmr) bit. there- fore the software must clear this bit before enabling the corresponding interrupt. .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 62 sept. 10, 2004; 6251-556-3ds micronas 2.9.8. control registers all control registers for the pwm are mapped in the sfr address space. their address and bit description are given below. note that the controller can write any time into these registers. however registers pwm_comp8_x, pwm_cpmp14_x and pwm_ cpmpext14_x, includ- ing the bits pwm_direct and pwm_pr are double buffered and values from shadow registers are only loaded into the main register in case timer overflows or timer is stopped (pwme = 00 h ) of 8 bit counter. overflow for 8 bit pwm occurs at the overflow of 6 bit counter and overflow for 14 bit counter occurs at the overflow. when any of the pwm channels is not used associ- ated compare register can be used as general purpose registers, except pwm_en and pwcompext14_0 bit 0 and 1. table 2?38: related registers register name bit name 7 6 5 4 3 2 1 0 pwm_en pe[7:0] pwm_comp8_0... pc80_[7:0] pwm_comp8_1 pc81_[7:0] pwm_comp8_2 pc82_[7:0] pwm_comp8_3 pc83_[7:0] pwm_comp8_4 pc84_[7:0] pwm_comp8_5 pc85_[7:0] pwm_comp14_0 pc140_[7:0] pwm_comp14_1 pc141_[7:0] pwm_compext14_0 pcx140_[7:0] pwm_compext14_1 pcx141_[7:0 pwm_cl pwc_[7:0] pwm_ch pwm_tmr ov pwc_[13:8] see section 3. on page 110 for detailed register description. .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 63 2.10. watchdog timer the watchdog timer is a 16 bit up counter which can be programed to clock by f wdt /2 or f wdt/ 128. the current count value of the watchdog timer is contained in the watchdog timer register wdt_high and wdt_low . which are read-only register. control and refresh func- tion of the wdt are controlled by wdt_refresh and wdt_ctrl . additionally the counter can be used as a general pur- pose timer in timer mode. the associated load register can be used either as load register or independently as a scratch pad register by the user. 2.10.1. input clock the input clock f wdt is the same as the cpu clock f sys divided by 12 (i.e. machine cycle). it is fed to the wdt either as divide-by-2 or divide-by-128 clock signal. the divider factor is determined by wdt_in ( wdt_ctrl ) equal 0 and 1 respectively. wdt_in has the same functionality in both watch dog mode and timer mode. 2.10.2. starting the watch dog timer wdt can be started if the wdt unit is in the watch dog mode (wdt_tmr = 0). wdt is started by setting the bit wdt_start in the wdt_ctrl register. immediately after the start (1 clock cycle) the reload value from the wdt_rel register is copied to the wdt_high . wdt_low is always reset to 0 upon start. data can be written to wdt_rel any time during nor- mal controller operation. data are only loaded to the counter upon start, refresh or watchdog reset (if wdt_narst is set). note that the counter registers are read only and can- not be directly written to by the controller. 2.10.3. refresh once the watch dog timer wdt is started it cannot be stopped by software. (note that while the wdt is run- ning any change to wdt_tmr bit would be ignored.) a refresh to the wdt is required before the counter over- flows. refreshing the wdt requires two instruction sequences whereby first instruction sets wdt_ref bit and the next instruction sets the wdt_start bit. (for example if there is a nop between these two instruc- tions, a refresh would be ignored). this double instruc- tion refresh minimize the chances of an unintentional reset of the watchdog timer. once set, the wdt_ref bit is reset by the hardware after three machine cycles. a refresh causes wdt_low to reset to 00 h and loads the reload value to from wdt_rel to wdt_high . 2.10.4. wdt reset if the software fails to refresh the wdt before the counter overflows after ffff h , an internally generated watchdog reset is performed. the watchdog timer reset differs only from the normal reset in that during normal reset all the wdt relevant bits in the three registers wdt_rel , wdt_refresh , wdt_control are reset to 00 h . the counter gets ini- tialized to 0000 h . in case of a watchdog reset, wdt_start and wdt_narst are not reset. the bit wdt_rst (read only) is set to indicate the source of the reset. in addition the wdt reset does not reset the pll and clock genera- tor. if the wdt_narst bit is set then the values in the wdt_rel are retained after the wdt reset. the counter starts with the same pre-scaler (wdt_in) and reload configuration as before reset. if wdt_narst is not set then upon watchdog reset, wdt_rel is reset to 00h and wdt_in to 0. after the wdt reset the counter starts again and must be refreshed by the microcontroller in order to avoid further wdt resets. duration of the wdt reset is sufficient to ensure the proper reset sequence. 2.10.5. power-down mode the wdt is shut off during power down mode along with the rest of the peripherals. in idle mode the wdt (in watchdog mode) is frozen, in timer mode it continues it?s operation. in power save mode psave (peri) the watchdog continues it?s oper- ation. any write access to this bit is ignored. if in timer mode the timer can be frozen by setting this bit. 2.10.6. time period the period between refreshing the watchdog timer and the next overflow can be determined by the following formula. pwdt = [2(1 + (wdt_in) .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 64 sept. 10, 2004; 6251-556-3ds micronas fig. 2?9: block diagram 2.10.7. wdt as general purpose timer the watch dog timer wdt counter can be used as a general purpose timer in timer mode. the associated load register can be used either as load register or independent scratch pad register for the programmer. this is achieved by setting wdt_tmr bit. wdt_tmr bit can only be set before starting the wdt timer. once the watchdog timer is started it is not pos- sible to switch to general purpose timer mode. if wdt_tmr bit is set then timer can be started using wtmr_strt bit. when the timer is started it ? resets the wtmr_ov overflow flag. ? loads the preload value from wdt_rel and starts counting up. upon overflow the wdt_rst bit is not set neither is internal watchdog reset initia ted. overflow is indicated by the bit wtmr_ov (r/w). overflow also sets the inter- rupt source bit cisr0 (wtmr). both of these bits are set by hardware and must be cleared by software. if the corresponding watchdog timer interrupt enable ie1 (ewt) bit is set then upon overflow the interrupt is initi- ated. after an overflow the timer starts to count from wdt_rel . it is possible for the microcontroller to stop the timer by resetting the wtmr_strt bit any time. while the timer is running, the wdt_tmr bit cannot be toggled. any write access to th is bit is ignored. to reset the wdt_tmr bit, either timer is stopped (wtmr_strt). however it is possible to stop the timer (wtmr_strt) and toggle the bit (wdt_tmr) with the same instruc- tion. table 2?39: maximum and minimum wdt overflow time period f system wdt_in wdt_rel p wdt min. 33.33 mhz 0 ff h 184.3 max. 33.33 mhz 1 00 h 3.02 s wdt_low wdt_tmr wdt_high :2 :128 m u x wdt_rst wdt_rel wdt_ctrl wdt_ref wdt_rel 8 wdt_in wdt f m u x wtmr__ov/int wdtrel_7 wdtrel_6 wdtrel_5 wdtrel_0 wdtrel_1 wdtrel_2 wdtrel_3 wdtrel_4 wdt_ctrl wdt_in wdt_start --- --- -- wdt_rst wdt_narst wdt_ref wdt_tmr wdt_refresh wtmr_strt wtmr_ov -- --- --- --- --- .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 65 2.11. analog digital converter (cadc) tvtpro includes a four channel 8-bit adc for control purposes. by means of these four input signals the controller is able to supervise the status of up to four analog signals and take actions if necessary. this analog signals can be connected to the port 2 inputs without any special configuration. if the port pins of port 2 are used as digital input, make sure that the input high level never exceeds vdda. the input range of the adc is fixed to the analog sup- ply voltage range (2.5 v nominal). the conversion is done continuously on all four chan- nels the results are stored in the sfrs cadc0 ? cadc3 and updated automatically every 46 2.11.1. power-down and wake-up during idle mode it is r equired to reduce the power consumption dramatically. in order to do this for the controller adc a special wake-up unit has been included. during this mode only the signal on input channel 1 is supervised. as soon as the input signal has fallen below a predefined level an interrupt is triggered and the system wakes up.t wo different levels are avail- able. the first one corresponds to (fullscale-4 lsb) the second one to (fullscale-16 lsb). the actual level can be selected by a control bit (adwule). nevertheless it is possible to send even this wake-up unit into power-down (for detailed description refer to section 2.3.20. on page 45). 2.11.2. registers table 2?40: related registers register name bit name 7 6 5 4 3 2 1 0 cadc0 cadco[7:0] cadc1 cadc1[7:0] cadc2 cadc2[7:0] cadc3 cadc3[7:0] cadcco adwule ad[3:0] cisr0 bit addressable l24 adc wtmr avs dvs pwtmr ahs dhs cisr1 bit addressable cc adw iex1 iex0 psave bit addressable cadc wakup sli_acq disp peri pcon smod pds idls sd gf1 gf0 pde idle see section 3. on page 110 for detailed register description. .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 66 sept. 10, 2004; 6251-556-3ds micronas 2.12. sync system 2.12.1. general description the display sync system is completely independent from the acquisition sync system (cvbs timing) and can either work as a sync master or as a sync slave system. talking about ?h/v-syncs? in this chapter and in section 2.13. on page 69 always refers to display related h/v syncs and ne ver to cvbs related sync timing. in sync slave mode tvtpro receives the synchroniza- tion information from two independent pins which deliver separate horizontal and vertical signals or a sandcastle impulse from which the horizontal and ver- tical sync signals are separated internally. due to the not line locked pixel clock generation it can process any possible horizontal and vertical sync frequency. in sync master mode tvtpro delivers separate hori- zontal and vertical signals with the same flexibility in the programming of these periods as in sync slave mode. 2.12.1.1. screen resolution the number of displayable pixels on the screen is defined by the pixel frequency (which is independent from horizontal frequency), the line period and number of lines within a field. the screen is divided in three dif- ferent regions: 2.12.1.1.1. blacklevel clamping area during horizontal and vertical blacklevel clamping, the black value (rgb = 000) is delivered on output side of tvtpro. inside this area the blank pin and cor pin are set to the same values which are defined as trans- parency for subclut0 (see also section 2.13.7.5. on page 88). this area is programmable in vertical direc- tion (in terms of lines) and in horizontal direction in terms of 33.33 mhz clock cycles. 2.12.1.1.2. border area the size of this area is defined by the sync delay regis- ters (sdh and sdv) and the size of the character dis- play area. the color and transparency of this area is defined by a color look up vector. see section 2.13.7. on page 79). fig. 2?10: tvtpro?s display timing horizontal blacklevel clamping h-sync delay vertical blacklevel clamping h-sync t h_clmp_e t h_clmp_b t h-period (hpr) character display area border variable count of character columns (33..64) variable height v-sync (ehcr) (sdh) bvcr vlr (bhcr) delay (sdv) (25 rows) evcr .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 67 2.12.1.1.3. character display area characters and their attributes which are displayed inside this area are free programmable according to the specifications of the display generator (see also section 2.13.2. on page 69). the start position of that area can be shifted in horizontal and vertical direction by programming the horizontal and vertical sync delay registers (sdh and sdv). the size of that area is defined by the instruction fs r in the display generator. registers which allow to se t up the screen and sync parameters are given in table 2?41. the user has to take care of setting pfr and sdh so that sdh/pfr is greater than 2 2.12.1.2. sync interrupts the sync unit delivers interrupts (horizontal and verti- cal interrupt) to the controller to support the recogni- tion of the frequency of an external sync source. these interrupts are related to the positive edge of the non delayed horizontal and vertical impulses which can be seen at pins hsync and vsync. table 2?41: overview on sync register settings parameters register min. value max. value step default sync control register scr no min/max general setup vl - lines / field vlr 1 line 1024 lines 1 line 625 lines t h-period - horizontal period hpr 15 table 2?42: possible display modes 50 hz/100 hz character display mode pclk t character display area 50 hz 40 .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 68 sept. 10, 2004; 6251-556-3ds micronas 2.12.1.3. related registers fig. 2?11: priority of clamp phase, screen background and pixel layer area. table 2?43: related registers register name bit name 7 6 5 4 3 2 1 0 scr1 reserved rgb_g_[1:0] cor_bl vsu[3:0] scr0 rgb_d_[1:0] hp vp int snc vcs mast cisr0 bit addressable l24 adc wtmr avs dvs pwtmr ahs dhs vlr1 odd_ev vsu[3:0) vlr[9:8] vlr0 vlr[7:0] hpr1 hpr[11:8] hpr0 hpr[7:0] sdv1 sdv[9:8] sdv0 sdv[7:0] sdh1 sdh[11:8] sdh0 sdh[7:0] hcr1 ehcr[7:0] hcr0 bhcr[7:0] bvcr bvcr[9:8] bvcr0 bvcr[7:0] evcr1 evcr[9:8] evcr0 evcr[7:0] sndcstl hys snd_v[2:0] snd_h[2:0] cscr0 enetclk enerclk pa_7 _alt vs_oe o_e_p3_0 o_e_pol see section 3. on page 110 for detailed register description. dhs is used as an interface from h input pin to software interrupt routines. dvs is used as an interface from v input pin to software interrupt routines. these interrupt routines can be used for detection of the frequency of an external sync source. it is set by the hw and must be reset by the sw. the clamp phase area has higher priority than the screen ba ckground area or the character display area and can be shifted i ndependent from any other register. screen background area pixel layer area clamp phase area h pulse h period - frame n video .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 69 2.13. display the display is based on the requirements for a level 1.5 teletext and powerful additional enhanced osd features. the display circuit reads the contents and attribute set- tings of the display memory and generates the rgb data for a tv back-end signal processing unit. the display can be synchronized to external h/v sync signals (slave mode) or can generate the synchroniza- tion signals by itself (master mode). the display can be synchronized to 50 hz as well as to 60 hz systems. interlaced display is supported for interlaced sync sources and non-interlaced ones. 2.13.1. display features ? teletext level 1.5 feature set ? rom character set to support all european lan- guages in parallel ? mosaic graphic character set ? parallel display attributes ? single/double width/height of characters ? variable flash rate ? programmable screen size (25 rows table 2?44: display memory organization of tvtpro row no. address i = 0d ? i = 39d 0 dispoint h + 0 h + i .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 70 sept. 10, 2004; 6251-556-3ds micronas 2.13.3. display memory the display memory is lo cated inside the internal xram. the start address of the display memory is at memory address dispoint h . this memory address is defined by the user due to a pointer. for each character posi- tion three bytes in the display memory are reserved. these three bytes are stored in a serial incremental order for each character and used to define the display attributes of each single character position. the com- plete amount of allocated display memory depends on the display resolution. in vertical direction the charac- ter display area is fixed to 25 rows. in horizontal direc- tion the character display area can be adjusted from 33 up to 64 columns. table 2?44 is an example for a character display area resolution of 25 rows and 40 columns. 2.13.4. parallel character attributes the character display area content of each character position is defined by a 3 byte character display word (cdw; see also section 2.13.9.1. on page 102) in dis- play memory. following formula helps to calculate a memory address of a character position (x ch , y ch ) depending on the count of characters in horizontal direction (defined in the binary parameters (disalh4 ? disalh0) h ) and a display start address dispoint h : table 2?45: character display word: ram location: display memory byte pos. bit name function remark 0 0 char0 used to choose a rom or drcs charac- ter drcs characters are defined by the user. up to 16 different colors can be used within one drcs; see also see section 2.13.4.1. 1 char1 2 char2 3 char3 4 char4 5 char5 6 char6 7 char7 1 8 char8 9 char9 10 flash control of flash modes see also section 2.13.4.4. 11 uh upper half double height see also section 2.13.4.5. 12 dh double height see also section 2.13.4.5. 13 dw double width see also section 2.13.4.6. 14 box control for boxes see also section 2.13.7.4. 15 clut0 bit0/clut select see also section 2.13.7.5. charaddress h dispoint h y ch disalh 4 disalh 0 () h 21 h + () x ch 3 h + () + = .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 71 2.13.4.1. access of characters the drcs characters and rom characters are accessed by a 10-bit character address inside the character display word (cdw; see also section 2.13.9.1. on page 102). 2.13.4.2. address range from 0 d to 767 d this address range can either be used to access rom characters or to access 1-bit drcs characters. see also section 2.13.5. on page 75 global display word (gdw). 2 16 clut1 bit1/clut select see also section 2.13.7.5. 17 clut2 bit2/clut select see also section 2.13.7.5. 18 fg0 foreground color vector only used for rom characters and 1-bit drcs characters; foreground-color is chosen if bit inside rom-mask/ram is set to ?1? see also section 2.13.7.5. 19 fg1 20 fg2 21 bg0 background color vector used for rom characters and 1-bit drcs characters; for 2-bit and 4-bit drcs characters only used in flash mode; background color is chosen if bit inside rom-mask/ram is set to ?0?; see also section 2.13.7.5.and section 2.13.4.4. 22 bg1 23 bg2 table 2?45: character display word: ram location: display memory, continued byte pos. bit name function remark table 2?46: definition of character access mode chaac description 0normal mode: address range 0 d - 767 d is used to access rom characters. 1 enhanced mode: address range 0 d - 767 d is used to access 1-bit drcs characters. .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 72 sept. 10, 2004; 6251-556-3ds micronas 2.13.4.3. address range from 768 d to 1023 d the address range from 768 d to 1023 d is reserved to address the drcs c haracters. this r ange is split into three parts for 1-bit drcs, 2-bit drcs and 4-bit drcs. the boundary between 1-bit drcs and 2-bit drcs as well as the boundary between 2-bit drcs and 4-bit drcs are defined by two boundary pointers inside the global display word (gdw) (see also section 2.13.5.) table 2?47: boundary pointer 1 drcs b1_3 drcs b1_2 drcs b1_1 drcs b1_0 description 0 0 0 0 boundary1 set to 768 d 0 0 0 1 boundary1 set to 784 d 0 0 1 0 boundary1 set to 800 d 0 0 1 1 boundary1 set to 816 d ?? 1 1 1 0 boundary1 set to 992 d 1 1 1 1 boundary1 set to 1008 d see also section 2.13.5. on page 75 / global display word (gdw) table 2?48: boundary pointer 2 drcs b2_3 drcs b2_2 drcs b2_1 drcs b2_0 description 0 0 0 0 boundary1 set to 768 d 0 0 0 1 boundary1 set to 784 d 0 0 1 0 boundary1 set to 800 d 0 0 1 1 boundary1 set to 816 d ?? 1 1 1 0 boundary1 set to 992 d 1 1 1 1 boundary1 set to 1008 d please notice: drcsb2_3 ? drcsb2_0 must be se t to a greater or a equal value than drcsb1_3 ? drcsb1_0. see also section 2.13.5. on page 75 / global display word (gdw) .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 73 below some examples can be found to show how the character addressing depends on the boundary defini- tions: 2.13.4.3.1. example 1 boundary pointer 1 set to 848 d boundary pointer 2 set to 928 d 2.13.4.3.2. example 2 boundary pointer1 set to 848 d boundary pointer2 set to 848d 2.13.4.3.3. example 3 boundary pointer 1 set to 768 d boundary pointer 2 set to 928 d 2.13.4.4. flash the bit flash inside the character display word (cdw; see also section 2.13.4.) is used to enable flash for a character. the meaning of the flash attribute is different for rom characters and 1-bit drcs characters in comparison to the meaning of flash for 2-bit and 4-bit drcs char- acters. for flash rate control see also the global attribute "flrate1 ? flrate0" in section 2.13.7.3.. 2.13.4.4.1. flash for rom characters and 1-bit drcs characters for rom characters and 1-bit drcs characters the enabled flash mode causes the foreground pixels to alternate between the foreground and background color vector. 2.13.4.4.2. flash for 2-bit and 4-bit drcs charac- ters for these characters the enabled flash mode causes the drcs pixels to alternate between the 2-bit/ 4-bit color vector and the background color vector which is defined by the parameters bg2 ? bg0 inside charac- ter display word (cdw; see also section 2.13.4. on page 70). character address description from to 768 d 847 d 1-bit drcs characters 848 d 991 d 2-bit drcs characters 928 d 1023 d 4-bit drcs characters character address description from to 768 d 847 d 1-bit drcs characters 848 d 1023 d 4-bit drcs characters character address description from to 768 d 927 d 2-bit drcs characters 928 d 1023 d 4-bit drcs characters flash description 0 steady (flash disabled) 1flash see also section 2.13.4. on page 70 / character display word (cdw) .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 74 sept. 10, 2004; 6251-556-3ds micronas 2.13.4.5. character indi vidual double height bit uh (upper half, double height) marks the upper part of a double height character. it is only active, if the dh bit (double height) is set to ?1?. table 2?49 shows the influence of the dh bit and the uh bit on the character ?a?. 2.13.4.6. character individual double width the bit dw (double width) marks the left half of a char- acter with double width. the character to its right will be overwritten by the right half. if the dw bit of the following character (here the ?x?) is also set to ?1?; the right half of the ?a? is overwritten by the left half of the ?x?. if a character is displayed in double width mode the attribute settings of the left character position are used to display the whole character. table 2?49: character individual double height dh uh display 0x 11 10 see also section 2.13.4. on page 70 / character display word (cdw) table 2?50: character individual double width dw bit display left character right character 00 10 11 01 see also section 2.13.4. on page 70 / character display word (cdw) .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 75 2.13.5. global osd attributes next to the parallel attributes stored inside character display word there are global attributes. the settings of the global attributes affect the full screen. the settings of the global osd attributes are stored in the global display word (gdw; see also section 2.13.5.) within 10 bytes in the xram. the location of the gdw is defined by a programmable pointer (see also section 2.13.9. on page 100). table 2?51: global osd attributes byte pos. bit name function cross reference 0 0 disalh0 count of display columns in horizontal direc- tion see also section 2.13.6. on page 79 1 disalh1 2 disalh2 3 disalh3 4 disalh4 5 progress used to enable progressive scan mode. see also section 2.13.7.8. on page 96 6 --- reserved. --- 7 --- reserved. --- 1 0 cursen enables cursor function. see also section 2.13.7. on page 79 1 curhor0 horizontal pixel shift of cursor to character position 2 curhor1 3 curhor2 4 curhor3 5 curver0 vertical pixel shift of cursor to character posi- tion 6 curver1 7 curver2 .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 76 sept. 10, 2004; 6251-556-3ds micronas 2 0 curver3 vertical pixel shift of cursor to character posi- tion see also section 2.13.7. on page 79 1poshor0 horizontal character position of cursor 2poshor1 3poshor2 4poshor3 5poshor4 6poshor5 7 posver0 vertical character position of cursor 3 0 posver1 1 posver2 2 posver3 3 posver4 4 glbt0_box1 used to enable transparency of box1. clut transparency of subclut0 can be overruled for destined pixels inside box1. see also section 2.13.7.4. on page 86 5 glbt1_box1 6 glbt2_box1 7 --- reserved. --- 4 0 brdcol0 color vector of border see also section 2.13.7.1. on page 83 1 brdcol1 2 brdcol2 3 brdcol3 4 brdcol4 5 brdcol5 6bla_box1 used to define the overruling transparency levels for box1. see also section 2.13.7.4. on page 86 7cor_box1 table 2?51: global osd attributes, continued byte pos. bit name function cross reference .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 77 5 0 gddh0 double height of the full screen see also section 2.13.7.2. on page 83 1 gddh1 2 gddh2 3 glbt0_box0 used to enable transparency of box0. clut transparency of subclut0 can be overruled for destined pixels inside box0. see also section 2.13.7.4. on page 86 4 glbt1_box0 5 glbt2_box0 6bla_box0 used to define the overruling transparency levels for box0. see also section 2.13.7.4. on page 86 7cor_box0 6 0 chadrc0 defines vertical resolution of drcs charac- ters. see also section 2.13.7.6. on page 94 1 chadrc1 2 chadrc2 3 charom0 defines vertical resolution of rom charac- ters. 4 charom1 5 charom2 6 chaac defines character access mode. see also section 2.13.4.1. on page 71 7 --- reserved. --- 7 0 drcsb1_0 used to define the boundary pointer 1 for drcs addressing. see also section 2.13.4.1. on page 71 1 drcsb1_1 2 drcsb1_2 3 drcsb1_3 4 drcsb2_0 used to define the boundary pointer 2 for drcs addressing. see also section 2.13.4.1. on page 71 5 drcsb2_1 6 drcsb2_2 7 drcsb2_3 table 2?51: global osd attributes, continued byte pos. bit name function cross reference .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 78 sept. 10, 2004; 6251-556-3ds micronas 8 0 shen enables shadow. see also section 2.13.7.7. on page 95 1 sheawe defines if east or west shadow is processed. 2 shcol0 defines the shadow color vector. 3 shcol1 4 shcol2 5 shcol3 6 shcol4 7 shcol5 9 0 curclut0 used to choose the foreground vector for the cursor (0 ? 63). see also section 2.13.7. on page 79 1 curclut1 2 curclut2 3flrate0 defines the flash rate for flashing characters. see also section 2.13.7.3. on page 85 4flrate1 5 hdwclutcor defines the level of cor for the colors of the hardwired clut. see also section 2.13.7.5. on page 88 6 hdwclutblank defines the level of blank for the colors of the hardwired clut. see also section 2.13.7.5. on page 88 7 --- reserved. --- table 2?51: global osd attributes, continued byte pos. bit name function cross reference .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 79 2.13.6. character display area resolution the count of rows of the character display area can be adjusted in a range from 33 to 64 columns in horizontal direction. in vertical direction the character display area is fixed to 25 rows. it depends on the settings for synchronization mode, pixel frequency and character matrix if all these columns are visible on the tube. the programmable parameters disalh4 to disalh0 are the binary representation of an offset value. this offset value plus 33 d gives the count of columns: table 2?52 shows some examples for the settings. 2.13.7. cursor the 2-bit color vector matrix of the cursor is stored in the xram. a programmable pointer is used, so that the matrix can be stored at any location inside the xram (see also section 2.13.9.3. on page 102). the cursor matrix has the same resolution as the char- acter matrix (see also section 2.13.7.6. on page 94). if the global display double height (see also section 2.13.7.2. on page 83) is set to double height, the rows which are displayed in double height the cur- sor is also displayed in double height. for rows which are displayed in normal height, the cursor is also dis- played in normal height. if cursor is displayed over two rows and one of these rows is displayed in double height, and the other is displayed in normal height, cur- sor is also partly displayed in double height and partly in normal height. cursor-pixels which are shifted to a non-visible row are also not displayed on the screen. the cursor can be shifted in horizontal and vertical direction pixel by pixel all over the character display area. the display position of the cursor is determined by a display column value, a display row value and on pixel level by a pixel shift in horizontal and vertical direction. the cursor can not be shifted more than one character height and one character width on pixel level. the cur- sor is clipped at the border of the display area. in full screen double height mode (see also section 2.13.7.2. on page 83) the cursor is also dis- played in double height. the pixel shift value is always related to a south-east shift. the pixel shift is determined by the parameters shown in table 2?54 and table 2?55 on page 80. table 2?52: character display area resolution disalh4 disalh3 disalh2 disalh1 disalh0 description 0000033 columns 0000134 columns 0001035 columns ? ? 0111148 columns 1000049 columns ? ? 1111063 columns 1111164 columns see also section 2.13.5. / global display word (gdw) table 2?53: setting of cursen to enable cursor mode cursen description 0 cursor mode disabled 1 cursor mode enabled see also section 2.13.5. on page 75 / global dis- play word (gdw) .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 80 sept. 10, 2004; 6251-556-3ds micronas the character position of the cursor is determined by the parameters shown in table 2?56 and table 2?57. character position and pixel position have to be changed in parallel. otherwise it may appear that the character position already has been changed to a new position, but the pixel positi on is still set to the former value. this may cause a ?jumping? cursor. to avoid this ?jumping? cursor there is a en_ld_gdw (enable load gdw) bit in the sfr bank. if this bit is set to ?0? the global display word can be changed without any effect on the screen and in consequence the cur- sor position can be changed without any effect on the screen. to bring the effect to character display area, the load bit has to be set to 1 for at least one v period (approximately 50 ms). table 2?54: horizontal cursor pixel offset within character matrix curhor3 curhor2 curhor1 curhor0 description 0 0 0 0 horizontal shift of 0 0 0 0 1 horizontal shift of 1 0 0 1 0 horizontal shift of 2 0 0 1 1 horizontal shift of 3 ?? 1 0 1 1 horizontal shift of 11 11xxnot allowed see also section 2.13.5. on page 75-global display word (gdw) table 2?55: vertical cursor pixel offset within character matrix curver3 curver2 curver1 curver0 description 0000vertical shift of 0 0001vertical shift of 1 0010vertical shift of 2 0011vertical shift of 3 ?? 1110vertical shift of 14 1111vertical shift of 15 see also section 2.13.5. on page 75-global display word (gdw) .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 81 the cursor is handled as a layer above the character display area. pixels of the 2-bit cursor bit plane which are set to ?00? are transparent to the osd/video layer below. so the cursor can be transparent to the osd (in case of no transparency of osd) or to video (in case of transparency of osd). table 2?56: horizontal character position of th e cursor within the character matrix pos hor5 pos hor4 pos hor3 pos hor2 pos hor1 pos hor0 description 000000horizontal character column 0 000001horizontal character column 1 ?? 111110horizontal character column 62 111111horizontal character column 63 see also section 2.13.5. on page 75-global display word (gdw) table 2?57: vertical character position of the cursor within the character matrix pos ver4 pos ver3 pos ver2 pos ver1 pos ver0 description 00000vertical character row 0 00001vertical character row 1 00010vertical character row 2 00011vertical character row 3 ? ? 1 1 1 1 0 vertical character row 30 1 1 1 1 1 vertical character row 31 see also section 2.13.5. on page 75-global display word (gdw) .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 82 sept. 10, 2004; 6251-556-3ds micronas example: fig. 2?12: positioning of hw cursor one out of 8 subcluts is used to display the cursor. the parameters curclut2 ? curclut0 are used to define the subclut to be used. for detailed information of clut access see section 2.13.7.5. on page 88 drcs-character pixel-shift: horizontal: vertical: stored at 896 d : 6 d 7 d column row 10 d 11 d 5 d 6 d character-row/column: horizontal: vertical: 10 d 5 d table 2?58: curclut2, curclut1, curclut0 cur clut2 cur clut1 cur clut0 description 000 used to select the subclut which is used for color look up of the cursor (0 ? 7) 001 010 011 ? 110 111 see also section 2.13.5. on page 75-global display word (gdw) .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 83 2.13.7.1. border color next to the character display area in which the charac- ters are displayed there is an area which is surround- ing the character display area . the visibility of this bor- der area depends on the width and height of the character display area. the user is free to define the color vector of this border. 2.13.7.2. full screen double height if double height is enabled for the full screen each line of the osd is repeated twice at the rgb output. as a result, characters which are normally displayed in nor- mal height, are now displayed in double height and characters which are normally displayed in double height are now displayed in quadruple height. row 0 and 24 are handled in a special way. if double height is selected for the full screen these two rows can be fixed to normal display (each line of these rows is repeated only once). in double height mode the user may want to start the processing of the display at row 12 and not at row 0. to decide this, three bits are used as a global attribute. table 2?59: border color settings brdcol5 brdcol4 brdcol3 brdcol2 brdcol1 brdcol0 description 000000 defines a color vector for the border; see also section 2.13.7.5. on page 88 000001 000010 000011 ? 111110 111111 see also section 2.13.5. on page 75-global display word (gdw) .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 84 sept. 10, 2004; 6251-556-3ds micronas table 2?60: full screen double height gddh2 gddh1 gddh0 display area 0 0 0 full screen normal height: 0 0 1 full screen double height: rows 0-11 are displayed in double height. row 24 is settled on bottom of display in normal height. 0 1 0 full screen double height: rows 12-23 are displayed in double height. row 24 is settled on bottom of display in normal height. 0 1 1 full screen double height: rows 13-24 are displayed in double height. row 0 is settled on top of display in normal height. 1 x x full screen double height: rows 1-12 are displayed in double height. row 0 is settled on top of display in normal height. see also section 2.13.5. on page 75-global display word (gdw) row-no. 0 row-no. 1 .... .... row-no. 23 row-no. 24 row-no. 11 row-no. 12 row-no. 0 row-no. 1 .... .... row-no. 23 row-no. 24 row-no. 11 row-no. 12 yg row-no. 0 row-no. 1 .... .... row-no. 23 row-no. 24 row-no. 11 row-no. 12 row-no. 0 row-no. 1 row-no. 11 row-no. 24 ... ... ... ... memory organization: display appearance: row-no. 0 row-no. 1 .... .... row-no. 23 row-no. 24 row-no. 11 row-no. 12 row-no. 12 row-no. 13 row-no. 23 row-no. 24 ... ... ... ... memory organization: display appearance: row-no. 0 row-no. 1 .... .... row-no. 23 row-no. 24 row-no. 11 row-no. 12 row-no. 13 row-no. 14 row-no. 24 ... ... ... ... memory organization: display appearance: row-no. 0 row-no. 0 row-no. 1 .... .... row-no. 23 row-no. 24 row-no. 11 row-no. 12 row-no. 1 row-no. 2 row-no. 12 ... ... ... ... memory organization: di sp l ay a ppearance: row-no. 0 .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 85 2.13.7.3. flash rate control this attribute is used to control the flash rate for the full screen. all the characters on the screen for which flash is enabled are flashing with same frequency and in same phase. table 2?61: flash rate control flrate1 flrate0 description 0 0 slow flash rate. the flash rate is derived from display v pulse. for 50 hz systems flash rate is approximately 0.5 hz. duty cycle is approximately 50%. 0 1 medium flash rate. the flash rate is derived from the v pulse. for 50 hz systems flash rate is approximately 1.0 hz. duty cycle is approximately 50%. 1 x fast flash rate. the flash rate is derived from the v pulse. for 50 hz systems flash rate is approximately 2.0 hz. duty cycle is approximately 50%. see also section 2.13.5. on page 75-global display word (gdw) .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 86 sept. 10, 2004; 6251-556-3ds micronas 2.13.7.4. transparency of boxes for characters which are using subclut0 the trans- parency which is defined for the whole clut (see also section 2.13.7.5. on page 88) can be overruled for foreground or background pixels. there are two differ- ent definitions for two box areas to define this overrul- ing. which of these two box transparencies is used, is selected character individual inside the bit box in cdw (character display word; see also section 2.13.4.) transparency definition for characters for box0: the cursor (see also section 2.13.7. on page 79) is not affected by these bits. table 2?62: transparency mode of box0 glbt2_box0 glbt1_box0 glbt0_box0 description x 0 0 box transparency is disabled for box0. for all pixels the global defi ned transparency of subclut0 is used. 0 0 1 box transparency is enabled for box0 for following pixels: foreground pixels of rom characters 0 1 0 box transparency is enabled for box0 for following pixels: foreground pixels of 1-bit drcs characters 0 1 1 box transparency is enabled for box0 for following pixels: foreground pixels of rom characters foreground pixels of 1-bit drcs characters 1 0 1 box transparency is enabled for box0 for following pixels: background pixels of rom characters 1 1 0 box transparency is enabled for box0 for following pixels: background pixels of 1-bit drcs characters 1 1 1 box transparency is enabled for box0 for following pixels: background pixels of rom characters background pixels of 1-bit drcs characters see also section 2.13.5. on page 75-global display word (gdw) .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 87 to decide the levels of cor and blank for box0 two global parameters are used. for characters which are using subclut0 there are two types of transparency which can be defined. which of these two box transparencies is used is defined character individual inside the bit box in cdw (character display word; see also section 2.13.4. on page 70). transparency definition for characters for which box is set to 1 and which are using subclut0. table 2?63: cor/blank polarity of box0 cor_box0 bla_box0 description 0 0 box transparency levels of cor and blank are overruled by: cor = 0; blank = 0 0 1 box transparency levels of cor and blank are overruled by: cor = 0; blank = 1 1 0 box transparency levels of cor and blank are overruled by: cor = 1; blank = 0 1 1 box transparency levels of cor and blank are overruled by: cor = 1; blank = 1 see also section 2.13.5. on page 75-global display word (gdw) table 2?64: transparency mode of box1 glbt2_box1 glbt1_box1 glbt0_box1 description x 0 0 box transparency is disabled for box1. 0 0 1 box transparency is enabled for box1 for following pixels: foreground pixels of rom characters 0 1 0 box transparency is enabled for box1 for following pixels: foreground pixels of 1-bit drcs characters 0 1 1 box transparency is enabled for box1 for following pixels: foreground pixels of rom characters foreground pixels of 1-bit drcs characters 1 0 1 box transparency is enabled for box1 for following pixels: background pixels of rom characters 1 1 0 box transparency is enabled for box1 for following pixels: background pixels of 1-bit drcs characters 1 1 1 box transparency is enabled for box1 for following pixels: background pixels of rom characters background pixels of 1-bit drcs characters see also section 2.13.5. on page 75-global display word (gdw) .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 88 sept. 10, 2004; 6251-556-3ds micronas to decide the levels of cor and blank for box1 two global parameters are used. 2.13.7.5. clut table 2?65: cor/blank polarity of box1 cor_box1 bla_box1 description 0 0 box transparency levels of cor and blank for box1 are overruled by: cor = 0; blank = 0 0 1 box transparency levels of cor and blank coming from clut0 inside box1 are overruled by: cor = 0; blank = 1 1 0 box transparency levels of cor and blank coming from clut0 inside box1 are overruled by: cor = 1; blank = 0 1 1 box transparency levels of cor and blank coming from clut0 inside box1 are overruled by: cor = 1; blank = 1 see also section 2.13.5. on page 75-global display word (gdw) table 2?66: cor/blank polarity setup for hardware clut during black clamp phase hdwclutcor hdwclutblank description 0 0 decides the polarity for cor and blank output for the hardwired clut entries 0-15 and the polarity of cor and blank during black clamp phase (see also section 2.12.1. on page 66): cor = 0 blank = 0 0 1 decides the polarity for cor and blank output for the hardwired clut entries 0-15 and the polarity of cor and blank during black clamp phase (see also section 2.12.1. on page 66): cor = 0 blank = 1 10 decides the polarity for cor and blank output for the hardwired clut entries 0-15 and the polarity of cor and blank during black clamp phase (see also section 2.12.1. on page 66): cor = 1 blank = 0 1 1 decides the polarity for cor and blank output for the hardwired clut entries 0-15 and the polarity of cor and blank during black clamp phase (see also section 2.12.1. on page 66): cor = 1 blank = 1 .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 89 the clut has a maximum width of 64 entries. the rgb values of the clut entries from 0-15 are hard- wired and can not be changed by software. the trans- parency for the hardwired clut values are set by a global attribute inside the global display word (gdw; see also section 2.13.5. on page 75). this global set- ting can be overruled inside of boxes (see also section 2.13.7.4. on page 86) the rgb values of the clut entries from 16 to 63 are free programmable. the rgb values of the clut are organized in the tvtpro xram in a incremental serial order. clut locations in side xram which are not used for osd can be used for any other storage pur- poses. the clut is divided in 8 subcluts with 8 entries for 1-bit drcs and rom characters. for 2-bit drcs characters the clut is divided in 8 subcluts with 4 entries. for 4-bit drcs characters the clut is divided in 4 subcluts with 16 different entries. the subcluts can be sele cted for each character position individual. for this three bits clut2, clut1 and clut0 are reserved inside the character display word (cdw; see also section 2.13.4. on page 70). clut entries from 0-15 are hardwired and can not be changed by the user. each of the 48 ram programmable clut locations have a width of 2 byte. these 2 bytes are used to define a 3 fig. 2?13: rgb/transparency memory format of clut fig. 2?13 shows the rbg/transparency memory for- mat of clut: bit 3 ? 0: 4-bit representation of blue value bit 7 ? 4: 4-bit representation of green value bit 11 ? 8: 4-bit representation of red value bit 12 directly fed to blank pin bit 13 directly fed to cor pin bit 14 reserved bit 15 reserved table 2?67: selection of used subclutx inside cdw for each individual character position clut2 clut1 clut0 meaning for rom character and 1-bit/2-bit drcs characters meaning for 4-bit drcs characters 000subclut0 is selected subclut0 is selected 001subclut1 is selected subclut1 is selected 010subclut2 is selected subclut2 is selected 011subclut3 is selected subclut3 is selected 100subclut4 is selected subclut0 is selected 101subclut5 is selected subclut1 is selected 110subclut6 is selected subclut2 is selected 111subclut7 is selected subclut3 is selected see also section 2.13.4. on page 70-character display word (cdw) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 red blue 0 1 2 3 0 1 2 30 1 2 3 green - - t1 t0 0 1 2 3 clutadress+1 clutadress+0 .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 90 sept. 10, 2004; 6251-556-3ds micronas table 2?68: organization of clut ram address clut entry clut no for rom, and 1-bit drcs character clut no for cursor clut no for 2-bit drcs character clut no for 4-bit drcs character hardwired clut no. entry no. entry no. entry no. entry 0 0 0 not available 0 not available 0 0 0r g b = 00 d 00 d 00 d not available 1 1 1 1 1 r g b = 15 d 00 d 00 d not available 2 2 2 2 2 r g b = 00 d 15 d 00 d not available 3 3 3 3 3 r g b = 15 d 15 d 00 d not available 4 4 not available 0 not available 04r g b = 00 d 00 d 15 d not available 5 5 1 1 5 r g b = 15 d 00 d 15 d not available 6 6 2 2 6 r g b = 00 d 15 d 15 d not available 7 7 3 3 7 r g b = 15 d 15 d 15 d not available 8 1 0 not available 0 not available 08r g b = 00 d 00 d 00 d not available 9 1 1 1 9 r g b = 07 d 00 d 00 d not available 10 2 2 2 10 r g b = 00 d 07 d 00 d not available 11 3 3 3 11 r g b = 07 d 07 d 00 d not available 12 4 not available 0 not available 012r g b = 00 d 00 d 07 d not available 13 5 1 1 13 r g b = 07d 00 d 07 d not available 14 6 2 2 14 r g b = 00 d 07 d 07 d not available 15 7 3 3 15 r g b = 07 d 07 d 07 d .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 91 clutpoint h + 00 h 16 2 0 0 0 0 0 1 0 software programmable clutpoint h + 02 h 17 1 1 1 1 software programmable clutpoint h + 04 h 18 2 2 2 2 software programmable clutpoint h + 06 h 19 3 3 3 3 software programmable clutpoint h + 08 h 20 4 1 0 1 0 4 software programmable clutpoint h + 0a h 21 5 1 1 5 software programmable clutpoint h + 0c h 22 6 2 2 6 software programmable clutpoint h + 0e h 23 7 3 3 7 software programmable clutpoint h + 10 h 24 3 0 2 0 2 0 8 software programmable clutpoint h + 12 h 25 1 1 1 9 software programmable clutpoint h + 14 h 26 2 2 2 10 software programmable clutpoint h + 16 h 27 3 3 3 11 software programmable clutpoint h + 18 h 28 4 3 0 3 0 12 software programmable clutpoint h + 1a h 29 5 1 1 13 software programmable clutpoint h + 1c h 30 6 2 2 14 software programmable clutpoint h + 1e h 31 7 3 3 15 software programmable table 2?68: organization of clut, continued ram address clut entry clut no for rom, and 1-bit drcs character clut no for cursor clut no for 2-bit drcs character clut no for 4-bit drcs character hardwired clut no. entry no. entry no. entry no. entry .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 92 sept. 10, 2004; 6251-556-3ds micronas clutpoint h + 20 h 32 4 0 4 0 4 0 2 0 software programmable clutpoint h + 22 h 33 1 1 1 1 software programmable clutpoint h + 24 h 34 2 2 2 2 software programmable clutpoint h + 26 h 35 3 3 3 3 software programmable clutpoint h + 28 h 36 4 5 0 5 0 4 software programmable clutpoint h + 2a h 37 5 1 1 5 software programmable clutpoint h + 2c h 38 6 2 2 6 software programmable clutpoint h + 2e h 39 7 3 3 7 software programmable clutpoint h + 30 h 40 5 0 6 0 6 0 8 software programmable clutpoint h + 32 h 41 1 1 1 9 software programmable clutpoint h + 34 h 42 2 2 2 10 software programmable clutpoint h + 36 h 43 3 3 3 11 software programmable clutpoint h + 38 h 44 4 7 0 7 0 12 software programmable clutpoint h + 3a h 45 5 1 1 13 software programmable clutpoint h + 3c h 46 6 2 2 14 software programmable clutpoint h + 3e h 47 7 3 3 15 software programmable table 2?68: organization of clut, continued ram address clut entry clut no for rom, and 1-bit drcs character clut no for cursor clut no for 2-bit drcs character clut no for 4-bit drcs character hardwired clut no. entry no. entry no. entry no. entry .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 93 2.13.7.5.1. clut access for rom characters/1-bit drcs characters for each pixel of a character a 1-bit background/fore- ground information is available. 1 out of 8 sub cluts can be selected by character display word (cdw; see also section 2.13.4.). 1 out of 8 color vectors can be selected as a foreground and background color vector by the character display word (cdw; see also section 2.13.4. on page 70). please notice table 2?68 on page 90. 2.13.7.5.2. clut access for 2-bit drcs characters 2-bit drcs characters are stored in the ram. within a 2-bit drcs character a 2-bit color vector information is available for each pixel. by this 2-bit information 1 out of 4 color vectors is selected from a subclut. 1 out of 8 subcluts is selected by character display word (cdw; see also section 2.13.4. on page 70). please notice table 2?68 on page 90. clutpoint h + 40 h 48 6 0 not available 0 not available 0 3 0 software programmable clutpoint h + 42 h 49 1 1 1 1 software programmable clutpoint h + 44 h 50 2 2 2 2 software programmable clutpoint h + 46 h 51 3 3 3 3 software programmable clutpoint h + 48 h 52 4 not available 0 not available 0 4 software programmable clutpoint h + 4a h 53 5 1 1 5 software programmable clutpoint h + 4c h 54 6 2 2 6 software programmable clutpoint h + 4e h 55 7 3 3 7 software programmable clutpoint h + 50 h 56 7 0 not available 0 not available 0 8 software programmable clutpoint h + 52 h 57 1 1 1 9 software programmable clutpoint h + 54 h 58 2 2 2 10 software programmable clutpoint h + 56 h 59 3 3 3 11 software programmable clutpoint h + 58 h 60 4 not available 0 not available 0 12 software programmable clutpoint h + 5a h 61 5 1 1 13 software programmable clutpoint h + 5c h 62 6 2 2 14 software programmable clutpoint h + 5e h 63 7 3 3 15 software programmable table 2?68: organization of clut, continued ram address clut entry clut no for rom, and 1-bit drcs character clut no for cursor clut no for 2-bit drcs character clut no for 4-bit drcs character hardwired clut no. entry no. entry no. entry no. entry .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 94 sept. 10, 2004; 6251-556-3ds micronas 2.13.7.5.3. clut access for 4-bit drcs characters 4-bit drcs characters are stored in the ram. within a 4-bit drcs character a 4-bit color vector information is available for each pixel. by this 1 out of 16 color vec- tors is selected from a subclut. one out of 4 subcluts are selected by character dis- play word (cdw; see also section 2.13.4. on page 70). please notice table 2?68 on page 90. 2.13.7.6. character resolution the character matrix of drcs characters can be adjusted in vertical direction from 9 lines up to 16 lines. in horizontal direction the character matrix is fixed to 12 pixels. the character matrix of the rom characters can also be adjusted in vertical direction from 9 lines up to 16 lines. in horizontal direction the rom character matrix is fixed to 12 pixels. the parameter charom is used to characterize the organization of rom characters. the parameter chadrc is used to characterize the organization of drcs characters and the vertical count of lines for a character row on output side. if the count of lines of rom characters is smaller than the count of drcs characters the lines of rom characters are filled up with background colored pixels. table 2?69: character resolution chadrc2 chadrc1 chadrc0 description 0009 lines 00110 lines 01011 lines 01112 lines 10013 lines 10114 lines 11015 lines 11116 lines see also section 2.13.5. on page 75-global display word (gdw) table 2?70: character matrix settings charom 2 charom 1 charom 0 description 0009 lines 00110 lines 01011 lines 01112 lines 10013 lines 10114 lines 11015 lines 11116 lines see also section 2.13.5. on page 75-global display word (gdw) .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 95 2.13.7.7. shadowing if shadowing is enabled the rom characters and 1-bit drcs characters of the characters are displayed by west shadow or east shadow. the color vector of the shadow is defined by software. the shadow color vec- tor has a width of 6 bit. the shadow feature is enabled by the bit shen. there are two options for shadowing, as shown in fig. 2?72 . example for a ?a? displayed in shadow mode: within one character matrix shadowing is only pro- cessed for the pixels which are belonging to that char- acter matrix. pixels of one character matrix can not generate a shadow inside a neighbored character matrix. fig. 2?14: processing of shadowing clut entries from 0-63 can be used as a shadow color vector as shown in table 2?73. table 2?71: shadow settings shen description 0 shadow disabled. 1 shadow for rom characters and 1-bit drcs characters. see also section 2.13.5. on page 75-global display word (gdw) table 2?72: shadow options sheawe description 0 east shadowing. 1 west shadowing. see also section 2.13.5. on page 75 / global dis- play word (gdw) shadowed pixel no shadow: east shadow: west shadow: background pixel foreground pixel table 2?73: shadow color vector settings shcol5 shcol4 shcol3 shcol2 shcol1 shcol0 description 000000 defines a color vector for shadowing see also section 2.13.7.5. on page 88 000001 ? 111110 111111 see also section 2.13.5. on page 75-global display word (gdw) .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 96 sept. 10, 2004; 6251-556-3ds micronas 2.13.7.8. progressive scan this feature is useful for tv-devices in which a frame consists of 1 field with 625 lines instead of 2 fields with 312.5 lines each. for this tv-fields on rgb-output lines are be repeated twice by enabling the progressive scan feature. this repetition of lines in vertical direction is only processed for lines inside the character display area. 2.13.8. drcs characters drcs characters are available in the xram. there are three different drcs colo r resolution formats avail- able: ? 1-bit per pixel drcs characters ? 2-bit per pixel drcs characters ? 4-bit per pixel drcs characters in which way this 1-bit, 2-bit or 4-bit color vector infor- mation is used to access the clut, see section 2.13.7.5. on page 88. 2.13.8.1. memory organization of drcs charac- ters the following examples are proceeded on the assump- tion that a height of 11 character lines is selected. the memory organization behaves the same for any other count of lines. fig. 2?15: allocation of pixels inside the character matrix table 2?74: progressive scan settings progress description 0 progressive scan support is disabled. 1 progressive scan support is enabled. see also section 2.13.5. on page 75-global display word (gdw) pixel0 pixel1 pixel2 pixel3 pixel4 pixel5 pixel6 pixel7 pixel8 pixel9 pixel10 pixel11 line0 line1 line2 line3 line4 line5 line6 line7 line8 line9 .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 97 each character starts at a new byte address. this causes, that for odd heights nibbles may be left free. table 2?75: 1-bit drcs characters char address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 character 1 drc1point h + 00 h char 1 char 1 char 1 char 1 char 1 char 1 char 1 char 1 line 0 line 0 line 0 line 0 line 0 line 0 line 0 line 0 pixel 0 pixel 1 pixel 2 pixel 3 p ixel 4 pixel 5 pixel 6 pixel 7 bit 0 bit 0 bit 0 bit 0 bit 0 bit 0 bit 0 bit 0 drc1point h + 01 h char 1 char 1 char 1 char 1 char 1 char 1 char 1 char 1 line 0 line 0 line 0 line 0 line 1 line 1 line 1 line 1 pixel 8 pixel 9 pixel 10 pixel 11 pixel 0 pixel 1 pixel 2 pixel 3 bit 0 bit 0 bit 0 bit 0 bit 0 bit 0 bit 0 bit 0 drc1point h + 02 h char 1 char 1 char 1 char 1 char 1 char 1 char 1 char 1 line 1 line 1 line 1 line 1 line 1 line 1 line 1 line 1 pixel 4 pixel 5 pixel 6 pixel 7 p ixel 8 pixel 9 pixel 10 pixel 11 bit 0 bit 0 bit 0 bit 0 bit 0 bit 0 bit 0 bit 0 ?? drc1point h + 10 h char 1 char 1 char 1 char 1 left free line 10 line 10 line 10 line 10 pixel 8 pixel 9 pixel 10 pixel 11 bit 0 bit 0 bit 0 bit 0 character 2 drc1point h + 11 h char 2 char 2 char 2 char 2 char 2 char 2 char 2 char 2 line 0 line 0 line 0 line 0 line 0 line 0 line 0 line 0 pixel 0 pixel 1 pixel 2 pixel 3 p ixel 4 pixel 5 pixel 6 pixel 7 bit 0 bit 0 bit 0 bit 0 bit 0 bit 0 bit 0 bit 0 ?? ? .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 98 sept. 10, 2004; 6251-556-3ds micronas table 2?76: 2-bit drcs characters char address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 character 1 drc2point h + 00 h char 1 char 1 char 1 char 1 char 1 char 1 char 1 char 1 line 0 line 0 line 0 line 0 line 0 line 0 line 0 line 0 pixel 0 pixel 0 pixel 1 pixel 1 p ixel 2 pixel 2 pixel 3 pixel 3 bit 0 bit 1 bit 0 bit 1 bit 0 bit 1 bit 0 bit 1 drc2point h + 01 h char 1 char 1 char 1 char 1 char 1 char 1 char 1 char 1 line 0 line 0 line 0 line 0 line 0 line 0 line 0 line 0 pixel 4 pixel 4 pixel 5 pixel 5 p ixel 6 pixel 6 pixel 7 pixel 7 bit 0 bit 1 bit 0 bit 1 bit 0 bit 1 bit 0 bit 1 drc2point h + 02 h char 1 char 1 char 1 char 1 char 1 char 1 char 1 char 1 line 0 line 0 line 0 line 0 line 0 line 0 line 0 line 0 pixel 8 pixel 8 pixel 9 pixel 9 p ixel 10 pixel 10 pixel 11 pixel 11 bit 0 bit 1 bit 0 bit 1 bit 0 bit 1 bit 0 bit 1 ?? drc2point h + 20 h char 1 char 1 char 1 char 1 char 1 char 1 char 1 char 1 line 10 line 10 line 10 line 10 line 10 line 10 line 10 line 10 pixel 8 pixel 8 pixel 9 pixel 9 p ixel 10 pixel 10 pixel 11 pixel 11 bit 0 bit 1 bit 0 bit 1 bit 0 bit 1 bit 0 bit 1 character 2 drc2point h + 21 h char 2 char 2 char 2 char 2 char 2 char 2 char 2 char 2 line 0 line 0 line 0 line 0 line 0 line 0 line 0 line 0 pixel 0 pixel 0 pixel 1 pixel 1 p ixel 2 pixel 2 pixel 3 pixel 3 bit 0 bit 1 bit 0 bit 1 bit 0 bit 1 bit 0 bit 1 ?? ? .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 99 table 2?77: 4-bit drcs characters char address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 character 1 drc4point h + 00 h char 1 char 1 char 1 char 1 char 1 char 1 char 1 char 1 line 0 line 0 line 0 line 0 l ine 0 line 0 line 0 line 0 pixel 0 pixel 0 pixel 0 pixel 0 p ixel 1 pixel 1 pixel 1 pixel 1 bit 0 bit 1 bit 2 bit 3 bit 0 bit 1 bit 2 bit 3 drc4point h + 01 h char 1 char 1 char 1 char 1 char 1 char 1 char 1 char 1 line 0 line 0 line 0 line 0 l ine 0 line 0 line 0 line 0 pixel 2 pixel 2 pixel 2 pixel 2 p ixel 3 pixel 3 pixel 3 pixel 3 bit 0 bit 1 bit 2 bit 3 bit 0 bit 1 bit 2 bit 3 drc4point h + 02 h char 1 char 1 char 1 char 1 char 1 char 1 char 1 char 1 line 0 line 0 line 0 line 0 l ine 0 line 0 line 0 line 0 pixel 4 pixel 4 pixel 4 pixel 4 p ixel 5 pixel 5 pixel 5 pixel 5 bit 0 bit 1 bit 2 bit 3 bit 0 bit 1 bit 2 bit 3 ?? drc4point h + 41 h char 1 char 1 char 1 char 1 char 1 char 1 char 1 char 1 line 10 line 10 line 10 line 10 line 10 line 10 line 10 line 10 pixel 10 pixel 10 pixel 10 pixel 10 pixel 11 pixel 11 pixel 11 pixel 11 bit 0 bit 1 bit 2 bit 3 bit 0 bit 1 bit 2 bit 3 character 2 drc4point h + 42 h char 2 char 2 char 2 char 2 char 2 char 2 char 2 char 2 line 0 line 0 line 0 line 0 l ine 0 line 0 line 0 line 0 pixel 0 pixel 0 pixel 0 pixel 0 p ixel 1 pixel 1 pixel 1 pixel 1 bit 0 bit 1 bit 2 bit 3 bit 0 bit 1 bit 2 bit 3 ?? ? .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 100 sept. 10, 2004; 6251-556-3ds micronas 2.13.9. memory organization the memory organization concept of the osd is based on a flexible pointer concept. all display mem- ory registers reside in the internal xram only. there are 4 bytes of sfr registers which are pointing to two pointer arrays inside the xram as shown in table 2?78 fig. 2?16: memory organization of on screen display vbi user data special function registers: pointarray0 pointarray1 drc1pointh drc2pointh drc4pointh dispointh clutpointh gdwcurpointh 1-bit drcs matrices 2-bit drcs matrices 4-bit drcs matrices display-memory clut cursor matrix clut gdw internal xram: table 2?78: pointers to start address of on-screen display registers inside xram sfr address name function xx h pointarray0 pointer to pointer array 0 xx h + 02 h pointarray1 pointer to pointer array 1 .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 101 these 2 sfr pointers are used to point to 2 table 2?79: memory pointers pointer array start address in array name function pointfield0 0 h (lbyte) 1 h (hbyte) dispointh pointer to display memory 2 h (lbyte) 3 h (hbyte) clutpoint pointer to clut 4 h (lbyte) 5 h (hbyte) gdwcurpointh pointer to gdw and cursor matrix pointfield1 0 h (lbyte) 1 h (hbyte) drc1pointh pointer 1-bit drcs matrices 2 h (lbyte) 3 h (hbyte) drc2pointh pointer 2-bit drcs matrices 4 h (lbyte) 5 h (hbyte) drc4pointh pointer 4-bit drcs matrices .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 102 sept. 10, 2004; 6251-556-3ds micronas 2.13.9.1. character display area the character display area consists of 3 bytes for each character position of the character display area. these three bytes are used to store the character display word as it is described in section 2.13.4. on page 70. the array is sorted in a incremental serial order com- ing from the top left character throughout the bottom right character of the character display area. for fur- ther information see section 2.13.2. on page 69. the length of this display memory area depends on the parameter settings of disalh0 ? disalh4. 2.13.9.2. clut area the clut area consist of 48 2.13.9.3. global display word/cursor the area of the global display word is fixed to 10 byte. all the global display relevant informations are stored inside global display word (gdw; see also section 2.13.5. on page 75). the cursor matrix for cur- sor display is stored after the global display word.see also section 2.13.2. on page 69. the length of the memory area of global display word is fixed to 10 byte. the length of the memory area of cursor matrix depends on the settings of chadrc2 ? chadrc0. 2.13.9.4. 1-bit/2-bit/4-bit drcs character in this area the pixel information of the dynamically reconfigurable characters is stored. for further infor- mation on the memory format refer to section 2.13.8. on page 96. the length of these areas depends on the settings of drcsb1_3 ? drcsb1_0 and the settings of drcsb2_3 ? drcsb2_0. .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 103 2.13.9.5. overview on the sfr registers other than the settings in the xram, sfr registers are used for osd control. table 2?80: sfr registers used for osd control sfr address name bit programmable width purpose f8 h en_ld_cur yes 1 bit used to avoid the download of the parameter settings of the gdw from the ram to the local display generator register bank. see also section : 0: download disabled. 1: download enabled. initial value: 0 f8 h en_dgout yes 1 bit used to disable/enable the output of the display gener- ator. if display generator is disabled the rgb outputs of the ic are set to black and the outputs blank and cor are set to. cor = enablecor blank = enablebla if display generator is enabled the display information rgb, cor and blank is generated according to the parameter settings in the xram. 0: display generator is disabled. 1: display generator is enabled. initial value: 0 f8 h dis_cor no 1 bit defines the level of the cor output if display generator is disabled. initial value: 0 f8 h dis_blank no 1 bit defines the level of the blank output if display genera- tor is disabled. initial value: 1 f3 h pointarray 1_1 no 6 bit defines a pointer to a pointer array. see also section 2.13.9. on page 100 initial value: 0 f4 h pointarray 1_0 no 8 bit defines a pointer to a pointer array. see also section 2.13.9. on page 100 initial value: 0 f5 h pointarray 0_1 no 6 bit defines a pointer to a pointer array. see also section 2.13.9. on page 100 initial value: 0 f6 h pointarray 0_0 no 8 bit defines a pointer to a pointer array. see also section 2.13.9. on page 100 initial value: 0 .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 104 sept. 10, 2004; 6251-556-3ds micronas 2.13.10. tvtext pro characters fig. 2?17: rom character matrices .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 105 fig. 2?18: rom character matrices .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 106 sept. 10, 2004; 6251-556-3ds micronas fig. 2?19: rom character matrices .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 107 fig. 2?20: rom character matrices .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 108 sept. 10, 2004; 6251-556-3ds micronas fig. 2?21: rom character matrices .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 109 2.14. d/a converter tvtpro uses a 3 2.14.1. related registers table 2?81: related registers register name bit name 7 6 5 4 3 2 1 0 scr1 reserved rgb_g[1:0] corbl vsu[3:0] psave bit addressable cadc wakup sli_acq disp peri pcon smod pds idls sd gf[1:0] pde idle see section 3. on page 110 for detailed register description. .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 110 sept. 10, 2004; 6251-556-3ds micronas 3. special function register (sfr) 3.1. sfr register block index 3.2. sfr register index table 3?1: sfr block index name page adc 128 crt 126 display 135 dsync 130 interrupt 121 micro 117 port 117 pwm 127 sfrif 129 uart 120 watchdog 125 table 3?2: sfr register bits index name page a[7:0] 120 a17 _p4_0 136 a18 _p4_1 136 a19 _p4_4 136 ac 120 acq_sta 130 acqon 130 ad[3:0] 128 adc 123 adw 124 adwule 128 ahs 124 avs 124 b[7:0] 120 bhcr[7:0] 133 bvcr[7:0] 133 bvcr[9:8] 133 c_nt0 119 c_nt1 118 cadc 129 cadc0[7:0] 128 cadc1[7:0] 128 cadc2[7:0] 128 cadc3[7:0] 128 caph[7:0] 126 capl[7:0] 126 cb[19:16] 119 cc 124 clk_src 129 cor_bl 131 cy 120 d[7:0] 120 dhs 124 dis_blank 135 dis_cor 135 disp 129 dph[7:0] 117 dpl[7:0] 117 dpsel[2:0] 117 dvs 124 e24 121 ead 121 eadw 121 eah 121 eal 121 eav 121 table 3?2: sfr register bits index, continued name page .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 111 ecc 121 edh 121 edv 121 ehcr[7:0] 132 en_dgout 135 en_ld_cur 135 enarw 136 enerclk 135 enetclk 135 epw 121 et0 121 et1 121 eu 121 evcr[7:0] 133 evcr[9:8] 133 ewt 121 ex0 121 ex0f 122 ex0r 122 ex1 121 ex12 121 ex13 121 ex18 121 ex19 121 ex1f 122 ex1r 122 ex20 121 ex21 121 ex6 121 exx0 121 exx0f 122 exx0r 122 exx1 121 table 3?2: sfr register bits index, continued name page exx1f 122 exx1r 122 f0 120 f1 120 fall 126 first 126 freqsel(1) 135 freqsel(2) 135 g0p0 122 g0p1 123 g1p0 122 g1p1 123 g2p0 122 g2p1 123 g3p0 122 g3p1 123 g4p0 122 g4p1 123 g5p0 122 g5p1 123 gate0 118 gate1 118 gf0 118 gf1 118 hp 131 hpr[11:8] 134 hpr[7:0] 134 hys 124 ib[19:16] 119 idle 118 idls 118 ie0 118 ie1 118 table 3?2: sfr register bits index, continued name page .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 112 sept. 10, 2004; 6251-556-3ds micronas iex0 124 iex1 124 int 131 intsrc1 136 intsrc1 136 it0 118 it1 118 l24 123 m0[1:0] 119 m1[1:0] 118 mast 132 mb[18:16] 119 mb[19] 119 mexsp[6:0] 119 minh[7:0] 126 minl[7:0] 126 mm 119 msiz[7:0] 120 mx[19] 119 mx[19] 119 mxm 119 nb[19:16] 119 o_e_p3_0 136 o_e_pol 136 odd_ev 133 oscpd 135 ov 126 ov 120 ov 127 p 120 p0[7:0] 117 p1[7:0] 117 p2[7:0] 117 table 3?2: sfr register bits index, continued name page p3[7:0] 117 p4[7:0] 117 p4_7 _alt 135 pc140[7:0] 127 pc141[7:0] 127 pc80[7:0] 127 pc81[7:0] 127 pc82[7:0] 127 pc83[7:0] 127 pc84[7:0] 127 pc85[7:0] 127 pcx140[7:2] 127 pcx141[7:2] 127 pde 118 pds 117 pe[7:0] 128 peri 129 pf[10:8] 130 pf[7:0] 130 plg 126 pll_res 129 plls 129 point0[13:8] 135 point0[7:0] 135 point1[13:8] 135 point1[7:0] 135 pr 126 pr1 126 pwc[13:8] 127 pwc[7:0] 127 pwm_tmr 127 pwtmr 124 rb8 120 table 3?2: sfr register bits index, continued name page .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 113 rel 126 relh[7:0] 126 rell[7:0] 126 ren 120 reserved 130 reserved 130 rgb_d[1:0] 131 rgb_g[1:0] 130 ri 120 rise 126 rs[1:0] 120 run 126 sd 118 sdh[11:8] 132 sdh[7:0] 132 sdv[7:0] 132 sdv[9:8] 132 sel 126 sli_acq 129 sm0 120 sm1 120 sm2 120 smod 117 snc 132 snd_h[2:0] 125 snd_v[5:3] 125 sp_[7:0] 117 start 126 tap 135 tap 135 tb8 120 tf0 118 tf1 118 table 3?2: sfr register bits index, continued name page th0[7:0] 119 th1[7:0] 119 ti 120 tl0[7:0] 119 tl1[7:0] 119 tr0 118 tr1 118 ub3 119 ub4 119 vbiadr[3:0] 130 vcs 132 vl[7:0] 134 vl[9:8] 134 vp 131 vs_oe 136 vsu[3:0] 131 vsu2[3:0] 134 wakup 129 wdt_in 125 wdt_narst 125 wdt_ref 125 wdt_rst 125 wdt_start 125 wdt_tmr 125 wdthi[7:0] 126 wdtlow[7:0] 125 wdtrel[7:0] 125 wtmr 123 wtmr_ov 125 wtmr_strt 125 table 3?2: sfr register bits index, continued name page .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 114 sept. 10, 2004; 6251-556-3ds micronas 3.3. sfr register address index table 3?3: sfr subaddress index sub data bits reset 7 6 5 4 3 2 1 0 80 1) p0[7:0] hff 81 sp_[7:0] h07 82 dpl[7:0] h00 83 dph[7:0] h00 84 2) dpsel[2:0] h00 87 smod pds idls sd gf1 gf0 pde idle h00 88 tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 h00 89 gate1 c_nt1 m1[1:0] gate0 c_nt0 m0[1:0] h00 8a tl0[7:0] h00 8b tl1[7:0] h00 8c th0[7:0] h00 8d th1[7:0] h00 90 p1[7:0] hff 94 cb[19:16] nb[19:16] h00 95 mm mb[18:16] ib[19:16] h00 96 mb[19] ub3 ub4 mx[19] mxm mx[19] h00 97 mexsp[6:0] h00 98 sm0 sm1 sm2 ren tb8 rb8 ti ri h00 99 d[7:0] h00 a0 p2[7:0] hff a8 eal ead eu et1 ex1 et0 ex0 h00 a9 edv eav exx1 ewt exx0 h00 aa edh eah ecc epw ex13 3) ex12 3) h00 ab eadw e24 ex21 3) ex20 3) ex19 3) ex18 3) h00 ac g5p0 g4p0 g3p0 g2p0 g1p0 g0p0 h00 ad exx1r exx1f exx0r exx0f ex1r ex1f ex0r ex0f h05 b0 p3[7:0] hff b1 wdtrel[7:0] h00 b2 wdt_in wdt_start wdt_narst wdt_rst h00 b3 wdt_ref wdt_tmr wtmr_strt wtmr_ov h00 b4 wdtlow[7:0] h00 b5 wdthi[7:0] h00 b7 rell[7:0] h00 b8 g5p1 g4p1 g3p1 g2p1 g1p1 g0p1 h00 b9 relh[7:0] h00 ba capl[7:0] h00 bb caph[7:0] h00 bc minl[7:0] h00 bd minh[7:0] h00 be ov pr plg rel run rise fall sel h00 .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 115 bf pr1 first start h00 c0 l24 adc wtmr avs dvs pwtmr ahs dhs h00 c1 pc80[7:0] h00 c2 pc81[7:0] h00 c3 pc82[7:0] h00 c4 pc83[7:0] h00 c5 pc84[7:0] h00 c6 pc85[7:0] h00 c7 pc140[7:0] h00 c8 cc adw iex1 iex0 h00 c9 pc141[7:0] h00 ca pcx140[7:2] h00 cb pcx141[7:2] h00 cc pwc[7:0] cd pwm_tmr ov pwc[13:8] ce pe[7:0] h00 d0 cy ac f0 rs[1:0] ov f1 p h00 d1 cadc0[7:0] h00 d2 cadc1[7:0] h00 d3 cadc2[7:0] h00 d4 cadc3[7:0] h00 d5 adwule ad[3:0] h00 d7 clk_src pll_res plls h00 d8 cadc wakup sli_acq disp peri h00 d9 acqon reserved acq_sta vbiadr[3:0] h00 da pf[10:8] h01 db pf[7:0] h48 dd enetclk 3) enerclk 3) p4_7_alt vs_oe o_e_p3_0 o_e_pol h00 de intsrc1 intsrc0 enarw a19_p4_4 a18_p4_1 a17_p4_0 h00 df hys snd_v[2:0] snd_h[2:0] h00 e0 a[7:0] h00 e1 reserved rgb_g[1:0] cor_bl vsu[3:0] h00 e2 rgb_d[1:0] hp vp int snc vcs mast h00 e3 sdv[9:8] h00 e4 sdv[7:0] h20 e5 sdh[11:8] h00 e6 sdh[7:0] h48 e7 ehcr[7:0] h0a e8 p4[7:0] h00 e9 bhcr[7:0] h00 ea bvcr[9:8] h00 eb bvcr[7:0] h00 table 3?3: sfr subaddress index, continued sub data bits reset 7 6 5 4 3 2 1 0 .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 116 sept. 10, 2004; 6251-556-3ds micronas ec evcr[9:8] h00 ed evcr[7:0] h04 ee odd_ev vsu2[3:0] vl[9:8] h02 ef vl[7:0] h71 f0 b[7:0] h00 f1 hpr[11:8] h08 f2 hpr[7:0] h55 f3 point1[13:8] h00 f4 point1[7:0] h06 f5 point0[13:8] h00 f6 point0[7:0] h00 f8 en_ld_cur en_dgout dis_cor dis_blank h00 f9 4) - fd 3) freqsel(1 ) freqsel(2 ) oscpd h80 ff msiz[7:0] 3) - ff msiz[7:0] h0f 1) addresses in bold are controller fix addresses. 2) all the empty bits in ?grey? are reserved 3) reserved. 4) these registers are for inte rnal use of the device. do not write in these locations. as a general rule: software should on ly write to the bits which it wants to cha nge. all other bits impl emented or not should be masked in order to avoid problems with future versions. table 3?3: sfr subaddress index, continued sub data bits reset 7 6 5 4 3 2 1 0 .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 117 3.4. sfr register description note: for compatibility reasons every undefined bit in a writeable register should be set to ?0?. unde- fined bits in a readable register should be treated as ?don?t care?! table 3?4: sfr register description name sub dir reset range function port p0 h80 rw hff port 0 p0[7:0] h80[7:0] rw 255 0..255 port 0 p1 h90 rw hff port 1 p1[7:0] h90[7:0] rw 255 0..255 port 1 p2 ha0 rw hff port 2 p2[7:0] ha0[7:0] rw 255 0..255 port 2 p3 hb0 rw hff port 3 p3[7:0] hb0[7:0] rw 255 0..255 port 3 p4 he8 rw port 4 p4[7:0] he8[7:0] rw 255 0..255 port 4 micro sp h81 rw h07 stack pointer sp_[7:0] h81[7:0] rw 7 0..255 stack pointer dpl h82 rw h00 data pointer low dpl[7:0] h82[7:0] rw 0 0..255 data pointer low byte dph h83 rw h00 data pointer high dph[7:0] h83[7:0] rw 0 0..255 data pointer high byte dpsel h84 rw h00 data pointer select dpsel[2:0] h84[2:0] rw 0 0..7 data pointer select selects one of eight data pointer pcon h87 rw h00 power control smod h87[7] rw 0 0..1 uart baud rate 0: normal baud rate. 1: double baud rate. pds h87[6] rw 0 0..1 power down start bit 0: power down mode not started. 1: power down mode started. the instruction that sets this bit is the last instruction before entering power down mode. additionally, this bit is protected by a delay cycle. power down mode is entered, if and only if bit pde was set by the pre- vious instruction. once set, this bit is cleared by hardware and always reads out a 0. dac, pll and oscillator are switched off during power down. the cadc is completely switc hed off (no wake up possible). .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 118 sept. 10, 2004; 6251-556-3ds micronas idls h87[5] rw 0 0..1 idle start bit 0: idle mode not started. 1: idle mode started. the instruction that sets this bit is the last instruction before entering idle mode. additionally, this bit is protected by a delay cycle. idle mode is entered, if and only if bit idle was set by the previous instruction. once set, this bit is cleared by hardware and always reads out a 0. sd h87[4] rw 0 0..1 slow-down bit 0: slow-down mode is disabled. 1: slow-down mode is enabled. this bit is set to indicate the exte rnal clock generating circuitry to slow down the frequency. this bit is not protected by a delay cycle. gf1 h87[3] rw 0 0..1 power control gf0 h87[2] rw 0 0..1 general purpose flag bits for user. pde h87[1] rw 0 0..1 power-down mode enable bit when set, a delay cycle is started. the following instruction can then set the device into power down mode. once set, this bit is cleared by hardware and always reads out a 0. idle h87[0] rw 0 0..1 idle start bit 0: idle mode not started. 1: idle mode started. the instruction that sets this bit is the last instruction before entering idle mode. additionally, this bit is protected by a delay cycle. idle mode is entered, if and only if bit idle was set by the previous instruction. once set, this bit is cleared by hardware and always reads out a 0. the cadc is switched off but the cadc-wake-up-unit is active. tcon h88 rw h00 timer/counter control tf1 h88[7] rw 0 0..1 timer 1 overflow flag. set by hardware on timer/counter overflow. cleared by hardware when processor vectors to interrupt routine. tr1 h88[6] rw 0 0..1 timer 1 run control bit. set/cleared by software to turn timer/counter on/off. tf0 h88[5] rw 0 0..1 timer 0 overflow flag. set by hardware on timer/counter overflow. cleared by hardware when processor vectors to interrupt routine. tr0 h88[4] rw 0 0..1 timer 0 run control bit. set/cleared by software to turn timer/counter on/off. ie1 h88[3] rw 0 0..1 interrupt 1 edge flag. set by hardware when external interrupt edge detected. cleared when interrupt processed. it1 h88[2] rw 0 0..1 interrupt 1 type control bit. set/cleared by software to specify falling edge/low level triggered external inte rrupts. it1 = 1 selects transition- activated external interrupts. ie0 h88[1] rw 0 0..1 interrupt 0 edge flag. set by hardware when external interrupt edge detected. cleared when interrupt processed. it0 h88[0] rw 0 0..1 interrupt 0 type control bit. set/cleared by software to specify falling edge/low level triggered external interrupts. it0 = 1 selects transition-activated external inter- rupts. tmod h89 rw h00 timer/counter mode control gate1 h89[7] rw 0 0..1 timer/ctr mode c_nt1 h89[6] rw 0 0..1 timer/ctr mode m1[1:0] h89[5:4] rw 0 0..3 timer/ctr mode gate0 h89[3] rw 0 0..1 gating control when set. timer/counter ?x is enabled only while ?intx pin is high and ?trx control pin is set. when cleared, timer ?x is enabled, whenever ?trx control bit is set. table 3?4: sfr register description, continued name sub dir reset range function .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 119 c_nt0 h89[2] rw 0 0..1 timer or counter selector. cleared for timer operation (input from inter- nal system clock). set for counter operation (input from ?tx input pin). m0[1:0] h89[1:0] rw 0 0..3 timer operating mode 00: 8048 timer: ?tlx serves as five-bit prescaler. 01: 16-bit timer/counter: ?thx and ?tlx are cascaded, there is no prescaler. 10: 8-bit auto-reload timer/counter: ?thx holds a value which is to be reloaded into ?tlx each time it overflows. 11: (timer 0) tl0 is an eight-bit timer/counter controlled by the stan- dard timer 0 control bits; th0 is an eight-bit timer only controlled by timer 1 control bits. (timer 1) timer/counter 1 is stopped. tl0 h8a rw h00 timer/counter 0 low byte tl0[7:0] h8a[7:0] rw 0 0..255 timer/ctr 0 low byte tl1 h8b rw h00 timer/counter 0 low byte tl1[7:0] h8b[7:0] rw 0 0..255 timer/ctr 1 low byte th0 h8c rw h00 timer/counter 0 high byte th0[7:0] h8c[7:0] rw 0 0..255 timer/ctr 0 high byte th1 h8d rw h00 timer/counter 1 high byte th1[7:0] h8d[7:0] rw 0 0..255 timer/ctr 1 high byte mex1 h94 rw h00 memory extension register 1 cb[19:16] h94[7:4] rw 0 0..15 current bank; read only nb[19:16] h94[3:0] rw 0 0..15 next bank; r/w mex2 h95 rw h00 memory extension register 2 mm h95[7] rw 0 0..1 memory mode; r/w; 1 = use mb mb[18:16] h95[6:4] rw 0 0..7 memory bank; r/w ib[19:16] h95[3:0] rw 0 0..15 interrupt bank; r/w mex3 h96 rw h00 memory extension register 3 mb[19] h96[7] rw 0 0..1 memory bank bit; r/wbit. see mex2. ub3 h96[6] rw 0 0..1 user bits; available to the user, for mmu they are dont care. ub4 h96[5] rw 0 0..1 user bits; available to the user, for mmu they are dont care. mx[19] h96[4] rw 0 0..1 movx-bank r/w if mxm is set, these bits will be us ed during external data moves into or from an externally connected data ram. mxm h96[3] rw 0 0..1 during external data memory accesses, the bits mx19 ? 16 are used as address lines a19 ? 16 instead of the current bank (cb). mx[18:16] h96[2:0] rw 0 0..7 movx-bank r/w if mxm is set, these bits will be us ed during external data moves into or from an externally connected data ram. mexsp h97 rw h00 memory extension stack pointer mexsp[6:0] h97[6:0] rw 0 0..255 memory ext stack pointer table 3?4: sfr register description, continued name sub dir reset range function .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 120 sept. 10, 2004; 6251-556-3ds micronas psw hd0 rw h00 program status word cy hd0[7] rw 0 0..1 program status word ac hd0[6] rw 0 0..1 program status word f0 hd0[5] rw 0 0..1 program status word rs[1:0] hd0[4:3] rw 0 0..3 program status word ov hd0[2] rw 0 0..1 program status word f1 hd0[1] rw 0 0..1 program status word p hd0[0] rw 0 0..1 program status word acc he0 rw h00 accumulator a[7:0] he0[7:0] rw 0 0..255 accumulator b hf0 rw h00 b register b[7:0] hf0[7:0] rw 0 0..255 b register msiz hff rw h0f scratch pad register msiz[7:0] hff[7:0] rw 15 0..255 scratch pad register uart scon h98 rw h00 serial control sm0 h98[7] rw 0 0..1 serial control sm1 h98[6] rw 0 0..1 serial control sm2 h98[5] rw 0 0..1 enables the multiprocessor communication feature in modes 2 and 3. in mode 2 or 3, if sm2 is set to 1 then ri will not be activated if the received 9th data bit (rb8) is 0. in mode 1, if sm2 = 1 then ri will not be activated if a valid stop bit was not received. in mode 0, sm2 should be 0. ren h98[4] rw 0 0..1 enables serial reception. se t by software to enable reception. cleared by software to disable reception. tb8 h98[3] rw 0 0..1 is the 9th data bit that wi ll be transmitted in modes 2 and 3. set or cleared by software as desired. rb8 h98[2] rw 0 0..1 in modes 2 and 3, is the 9th data bit that was received. in mode 1, if sm2 = 0, rb8 is the stop bit that was received. in mode 0, rb8 is not used. ti h98[1] rw 0 0..1 is the transmit interrupt flag. set by hardware at the end of the 8th bit time in mode 0, or at the beginning of the stop bit in the other modes, in any serial transmission. must be cleared by software. ri h98[0] rw 0 0..1 is the receive interrupt flag. set by hardware at the end of the 8th bit time in mode 0, or halfway through stop bit time in the other modes, in any serial reception. must be cleared by software. sbuf h99 rw h00 d[7:0] h99[7:0] rw 0 0..255 serial data buffer table 3?4: sfr register description, continued name sub dir reset range function .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 121 interrupt ien0 ha8 rw h00 interrupt enable 0 eal ha8[7] rw 0 0..1 enable all interrupts when set to ?0, all interrupts are disabled. when set to ?1, interrupts are individually enabled/disabled according to their respective bit selection. ead ha8[5] rw 0 0..1 enable or disable analog to digital convertor interrupt eu ha8[4] rw 0 0..1 enable or disable uart interrupt et1 ha8[3] rw 0 0..1 enable or disable timer 1 overflow interrupt ex1 ha8[2] rw 0 0..1 enable or disable external interrupt 1 et0 ha8[1] rw 0 0..1 enable or disable timer 0 overflow interrupt ex0 ha8[0] rw 0 0..1 enable or disable external interrupt 0 ien1 ha9 rw h00 interrupt enable 1 edv ha9[5] rw 0 0..1 enable or disable display v-sync eav ha9[4] rw 0 0..1 enable or disable acquisition v-sync exx1 ha9[3] rw 0 0..1 enable or disable extra external interrupt 1 ewt ha9[2] rw 0 0..1 enable or disable watchdog in timer mode exx0 ha9[1] rw 0 0..1 enable or disable extra external interrupt 0 ex6 ha9[0] reserved ien2 haa rw h00 interrupt enable 2 edh haa[5] rw 0 0..1 enable or disable display h-sync eah haa[4] rw 0 0..1 enable or disable acquisition h-sync ecc haa[3] rw 0 0..1 enable or disable channel change interrupt epw haa[2] rw 0 0..1 enable or disable pwm in timer mode ex13 haa[1] reserved ex12 haa[0] reserved ien3 hab rw h00 interrupt enable 3 eadw hab[5] rw 0 0..1 enable or disable analog to digital wake up unit e24 hab[4] rw 0 0..1 enable or disable line 24 interrupt ex21 hab[3] reserved ex20 hab[2] reserved ex19 hab[1] reserved ex18 hab[0] reserved table 3?4: sfr register description, continued name sub dir reset range function .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 122 sept. 10, 2004; 6251-556-3ds micronas ip1 hac rw h00 interrupt priority 1 g5p0 hac[5] rw 0 0..1 interrupt group priority level as follows: 0 0: interrupt group x is set to priority level 0 (lowest). 0 1: interrupt group x is set to priority level 1. 1 0: interrupt group x is set to priority level 2. 1 1: interrupt group x is set to priority level 3 (highest). g4p0 hac[4] rw 0 0..1 interrupt group priority level as follows: 0 0: interrupt group x is set to priority level 0 (lowest). 0 1: interrupt group x is set to priority level 1. 1 0: interrupt group x is set to priority level 2. 1 1: interrupt group x is set to priority level 3 (highest). g3p0 hac[3] rw 0 0..1 interrupt group priority level as follows: 0 0: interrupt group x is set to priority level 0 (lowest). 0 1: interrupt group x is set to priority level 1. 1 0: interrupt group x is set to priority level 2. 1 1: interrupt group x is set to priority level 3 (highest). g2p0 hac[2] rw 0 0..1 interrupt group priority level as follows: 0 0: interrupt group x is set to priority level 0 (lowest). 0 1: interrupt group x is set to priority level 1. 1 0: interrupt group x is set to priority level 2. 1 1: interrupt group x is set to priority level 3 (highest). g1p0 hac[1] rw 0 0..1 interrupt group priority level as follows: 0 0: interrupt group x is set to priority level 0 (lowest). 0 1: interrupt group x is set to priority level 1. 1 0: interrupt group x is set to priority level 2. 1 1: interrupt group x is set to priority level 3 (highest). g0p0 hac[0] rw 0 0..1 interrupt group priority level as follows: 0 0: interrupt group x is set to priority level 0 (lowest). 0 1: interrupt group x is set to priority level 1. 1 0: interrupt group x is set to priority level 2. 1 1: interrupt group x is set to priority level 3 (highest). ircon had rw h05 interrupt control register exx1r had[7] rw 0 0..1 if set, externalx 1-interrupt detection on rising edge at pin p3.7 exx1f had[6] rw 0 0..1 if set, externalx 1-interrupt detection on falling edge at pin p3.7 exx0r had[5] rw 0 0..1 if set, externalx 0-interrupt detection on rising edge at pin p3.1 exx0f had[4] rw 0 0..1 if set, externalx 0-interrupt detection on falling edge at pin p3.1 ex1r had[3] rw 0 0..1 if set, external 1-interrupt detection on rising edge at pin p3.3 ex1f had[2] rw 1 0..1 if set, external 1-interrupt detection on falling edge at pin p3.3 ex0r had[1] rw 0 0..1 if set, external 0-interrupt detection on rising edge at pin p3.2 ex0f had[0] rw 1 0..1 if set, external 0-interrupt detection on falling edge at pin p3.2 table 3?4: sfr register description, continued name sub dir reset range function .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 123 ip0 hb8 rw h00 interrupt priority 0 g5p1 hb8[5] rw 0 0..1 interrupt group priority level as follows: 0 0: interrupt group x is set to priority level 0 (lowest). 0 1: interrupt group x is set to priority level 1. 1 0: interrupt group x is set to priority level 2. 1 1: interrupt group x is set to priority level 3 (highest). g4p1 hb8[4] rw 0 0..1 interrupt group priority level as follows: 0 0: interrupt group x is set to priority level 0 (lowest). 0 1: interrupt group x is set to priority level 1. 1 0: interrupt group x is set to priority level 2. 1 1: interrupt group x is set to priority level 3 (highest). g3p1 hb8[3] rw 0 0..1 interrupt group priority level as follows: 0 0: interrupt group x is set to priority level 0 (lowest). 0 1: interrupt group x is set to priority level 1. 1 0: interrupt group x is set to priority level 2. 1 1: interrupt group x is set to priority level 3 (highest). g2p1 hb8[2] rw 0 0..1 interrupt group priority level as follows: 0 0: interrupt group x is set to priority level 0 (lowest). 0 1: interrupt group x is set to priority level 1. 1 0: interrupt group x is set to priority level 2. 1 1: interrupt group x is set to priority level 3 (highest). g1p1 hb8[1] rw 0 0..1 interrupt group priority level as follows: 0 0: interrupt group x is set to priority level 0 (lowest). 0 1: interrupt group x is set to priority level 1. 1 0: interrupt group x is set to priority level 2. 1 1: interrupt group x is set to priority level 3 (highest). g0p1 hb8[0] rw 0 0..1 interrupt group priority level as follows: 0 0: interrupt group x is set to priority level 0 (lowest). 0 1: interrupt group x is set to priority level 1. 1 0: interrupt group x is set to priority level 2. 1 1: interrupt group x is set to priority level 3 (highest). cisr0 hc0 rw h00 central interrupt service 0 l24 hc0[7] rw 0 0..1 1: line 24 start interrupt occurred, source bit set by hardware, source bit must be reset by software after servicing the interrupt. 0: interrupt has not occurred. adc hc0[6] rw 0 0..1 1: analog to digital conversion complete source bit set by hardware. source bit must be reset by software after servicing the interrupt. 0: interrupt has not occurred. wtmr hc0[5] rw 0 0..1 1: watchdog in timer mode overflow source bit set by hardware. source bit must be reset by software after servicing the interrupt. 0: interrupt has not occurred. on reset this bit is initialized to 0, however if timer mode is selected and timer is running, every over flow of timer will set this bit. therefore software must clear this bit before enabling the corresponding interrupt. table 3?4: sfr register description, continued name sub dir reset range function .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 124 sept. 10, 2004; 6251-556-3ds micronas avs hc0[4] rw 0 0..1 1: acquisition vertical sy nc interrupt source bit set by hardware. source bit must be reset by software after servicing the interrupt. 0: interrupt has not occurred. dvs hc0[3] rw 0 0..1 1: display vertical sync interrupt source bit set by hardware. source bit must be reset by software after servicing the interrupt. 0: interrupt has not occurred. pwtmr hc0[2] rw 0 0..1 1: pwm in timer mode overflow interrupt source bit set by hardware. source bit must be reset by software after servicing the interrupt. 0: interrupt has not occurred. on reset this bit is initialized to 0,however if timer mode is selected and timer is running, every over flow of timer will set this bit. therefore software must clear this bit before enabling the corresponding interrupt. ahs hc0[1] rw 0 0..1 1: acquisition horizontal sync interrupt source bit set by hardware. source bit must be reset by software after servicing the interrupt. 0: interrupt has not occurred. dhs hc0[0] rw 0 0..1 1: display horizontal sync interrupt source bit set by hardware. source bit must be reset by software after servicing the interrupt. 0: interrupt has not occurred. cisr1 hc8 rw h00 central interrupt service 1 cc hc8[7] rw 0 0..1 1: channel change interrupt source bit set by hardware. source bit must be reset by software after servicing the interrupt. 0: interrupt has not occurred. adw hc8[6] rw 0 0..1 1: adc wake up interrupt source bit set by hardware. source bit must be reset by software after servicing the interrupt. 0: interrupt has not occurred. iex1 hc8[1] rw 0 0..1 external extra interrupt 1 edge flag. set by hardware when external interrupt edge detected. must be cleared by software. port p3.7 must be in input mode to use this interrupt. iex0 hc8[0] rw 0 0..1 external extra interrupt 0 edge flag. set by hardware when external interrupt edge detected. must be cleared by software. port p3.1 must be in input mode to use this interrupt. sndcstl hdf rw sandcastle hys hdf[6] rw definition of hysteres is (slave mode/sandcastle input) defines the voltage range for the hysteresis: 0: hysteresis set to 0.325 v. 1: hysteresis set to 0.150 v. table 3?4: sfr register description, continued name sub dir reset range function .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 125 snd_v[2:0] hdf[5:3] rw slicing level vertical sync-pulses (slave mode/sandcastle input) to fit the requirements of various appl ications the input circuit of the sandcastle decoder is free programma ble. the slicing levels for the vertical pulses can be varied in a range from 0.67 v up to 1.83 v in steps of about 0.16 v: 000: vertical slicing level set to 0.67 v. 001: vertical slicing level set to 0.83 v. 010: vertical slicing level set to 1.00 v. 011: vertical slicing level set to 1.17 v. 100: vertical slicing level set to 1.33 v. 101: vertical slicing level set to 1.50 v. 110: vertical slicing level set to 1.67 v. 111: vertical slicing level set to 1.83 v. these are nominal values. they may also differ with supply voltage. snd_h[2:0] hdf[2:0] rw slicing level horizontal sync-pulses (slave mode/sandcastle input) to fit the requirements of various appl ications the input circuit of the sandcastle decoder is free programma ble. the slicing levels for the horizontal pulses can be varied in a range from 1.33 v up to 2.50 v in steps of about 0.16 v: 000: horizontal slicing level set to 1.33 v 001: horizontal slicing level set to 1.50 v 010: horizontal slicing level set to 1.67 v 011: horizontal slicing level set to 1.83 v 100: horizontal slicing level set to 2.00 v 101: horizontal slicing level set to 2.17 v 110: horizontal slicing level set to 2.33 v 111: horizontal slicing level set to 2.50 v these are nominal values. they may also differ with supply voltage. watchdog wdt_rel hb1 rw h00 watchdog reload wdtrel[7:0] hb1[7:0] rw 0 0..255 reload value of the watchdog timer (also in timer-mode), is loaded in the upper 8 bit of the watchdog counter at wdt-start and ?reload and also at timer start. wdt_ctrl hb2 rw h00 watchdog control wdt_in hb2[7] rw 0 0..1 watchdog control wdt_start hb2[6] rw 0 0..1 watchdog control wdt_narst hb2[5] rw 0 0..1 watchdog control wdt_rst hb2[4] rw 0 0..1 watchdog control wdt_refresh hb3 rw h00 watchdog refresh wdt_ref hb3[7] rw 0 0..1 watchdog refresh wdt_tmr hb3[6] rw 0 0..1 watchdog refresh wtmr_strt hb3[5] rw 0 0..1 watchdog refresh wtmr_ov hb3[4] rw 0 0..1 watchdog refresh wdt_low hb4 rw h00 wdt timer low wdtlow[7:0] hb4[7:0] rw 0 0..255 counter value of the watchdog timer; low byte. table 3?4: sfr register description, continued name sub dir reset range function .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 126 sept. 10, 2004; 6251-556-3ds micronas wdt_high hb5 rw h00 wdt timer high wdthi[7:0] hb5[7:0] rw 0 0..255 counter value of the watchdog timer; high byte. crt crt_rell hb7 rw h00 crt reload low rell[7:0] hb7[7:0] rw 0 0..255 crt reload low byte crt_relh hb9 rw h00 crt reload high relh[7:0] hb9[7:0] rw 0 0..255 crt reload high byte crt_capl hba rw h00 crt capture low capl[7:0] hba[7:0] rw 0 0..255 crt capture low byte crt_caph hbb rw h00 crt capture high caph[7:0] hbb[7:0] rw 0 0..255 crt capture high byte crt_mincapl hbc rw h00 crt min capture low minl[7:0] hbc[7:0] rw 0 0..255 crt min capture low crt_mincaph hbd rw h00 crt min capture high minh[7:0] hbd[7:0] rw 0 0..255 crt min capture high crt_con0 hbe rw h00 crt control 0 ov hbe[7] rw 0 0..1 will be set by hardware, if counter overflow has occurred; must be cleared by software. pr hbe[6] rw 0 0..1 if cleared, 2-bit pres caler; if set, 3-bit prescaler. plg hbe[5] rw 0 0..1 if set, timer polling mode selected, capture function is automatically disabled, reading capture registers will now show current timer value. rel hbe[4] rw 0 0..1 if set, counter will be re loaded simultaneously with capture event. run hbe[3] rw 0 0..1 run/stop the crt counter. rise hbe[2] rw 0 0..1 capture (and if rel = ?1, reload) on rising edge. fall hbe[1] rw 0 0..1 capture (and if rel = ?1, reload) on falling edge. sel hbe[0] rw 0 0..1 if set, p3.3 is selected for capture input, otherwise p3.2. crt_con1 hbf rw h00 crt control 1 pr1 hbf[2] rw 0 0..1 1: divides input further by 8. 0: not divided by 8. first hbf[1] rw 0 0..1 1: indicates first event. 0: indicates not first event. start hbf[0] rw 0 0..1 1: controller sets this bit enter the ssu mode and to indicate it is expecting a new telegram. when an event occurs caputr unit sets first bit. upon next event, hardware re sets the first bit and interrupt is generated based on min_cap register. 0: not ssu mode. table 3?4: sfr register description, continued name sub dir reset range function .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 127 pwm pwm_comp8_0 hc1 rw h00 pwm 8 bit compare 0 pc80[7:0] hc1[7:0] rw 0 0..255 pwm 8bit compare 0 pwm_comp8_1 hc2 rw h00 pwm 8 bit compare 1 pc81[7:0] hc2[7:0] rw 0 0..255 pwm 8bit compare 1 pwm_comp8_2 hc3 rw h00 pwm 8 bit compare 2 pc82[7:0] hc3[7:0] rw 0 0..255 pwm 8bit compare 2 pwm_comp8_3 hc4 rw h00 pwm 8 bit compare 3 pc83[7:0] hc4[7:0] rw 0 0..255 pwm 8bit compare 3 pwm_comp8_4 hc5 rw h00 pwm 8 bit compare 4 pc84[7:0] hc5[7:0] rw 0 0..255 pwm 8bit compare 4 pwm_comp8_5 hc6 rw h00 pwm 8 bit compare 5 pc85[7:0] hc6[7:0] rw 0 0..255 pwm 8bit compare 5 pwm_comp14_0 hc7 rw h00 pwm 14 bit compare 0 pc140[7:0] hc7[7:0] rw 0 0..255 pwm 14bit compare 0 this bits define the high time of t he output. if all bits are 0, the high time is 0 internal clocks. if all bits are 1, the high time of a base cycle is 255 internal clocks. pwm_comp14_1 hc9 rw h00 pwm 14 bit compare 1 pc141[7:0] hc9[7:0] rw 0 0..255 pwm 14bit compare 1 this bits define the high time of t he output. if all bits are 0, the high time is 0 internal clocks. if all bits are 1, the high time of a base cycle is 255 internal clocks. pwm_compext14_0 hca rw h00 pwm 14 bit compext 0 pcx140[7:2] hca[7:2] rw 0 0..63 pwm 14bit comp ext 0 pwm_compext14_1 hcb rw h00 pwm 14 bit compext 1 pcx141[7:2] hcb[7:2] rw 0 0..63 pwm 14bit comp ext 1 pwm_cl hcc rw pwm counter low byte pwc[7:0] hcc[7:0] rw 0..255 pwm counter low byte pwm_ch hcd rw pwm counter high byte pwm_tmr hcd[7] rw 0 0..1 start/stop timer when all pwm channels are disabled. if this bit is set, the pwm timer will be reset and starts counting. if this bit is cleared, the pwm timer stops. the pwm_tmr bit could not be written (set) if one of the pwm channels is enabled (pwm_en not all zero). pwm_en register could not be writt en (set) if the pwm_tmr bit is set. ov hcd[6] rw 0 0..1 overflow bit for the timer mode. pwc[13:8] hcd[5:0] rw 0..63 pwm counter high byte table 3?4: sfr register description, continued name sub dir reset range function .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 128 sept. 10, 2004; 6251-556-3ds micronas pwm_en hce rw h00 pwm channel enable pe[7:0] hce[7:0] rw 0 0..255 pwm channel enable 0: the corresponding pwm-channel is disabled. p1.i functions as normal bidirectional i/o-port. 1: the corresponding pwm-channel is enabled. pe0 ? pe5 are channels with 8-bit resolution, wh ile pe6 and pe7 are channels with 14-bit resolution. adc cadc0 hd1 rw h00 adc channel 0 result cadc0[7:0] hd1[7:0] rw 0 0..255 adc result of channel 0 after finishing the a to d conversi on the processor is informed by means of an interrupt. the interrupt service routine can now take the conversion result of channel 1 fr om cadc0. the result will be available for about 46 ms after the interrupt. cadc1 hd2 rw h00 adc channel 1 result cadc1[7:0] hd2[7:0] rw 0 0..255 adc result of channel 1 after finishing the a to d conversi on the processor is informed by means of an interrupt. the interrupt service routine can now take the conversion result of channel 2 fr om cadc1. the result will be available for about 46 ms after the interrupt. cadc2 hd3 rw h00 adc channel 2 result cadc2[7:0] hd3[7:0] rw 0 0..255 adc result of channel 2 after finishing the a to d conversi on the processor is informed by means of an interrupt. the interrupt service routine can now take the conversion result of channel 3 fr om cadc2. the result will be available for about 46 ms after the interrupt. cadc3 hd4 rw h00 adc channel 3 result cadc3[7:0] hd4[7:0] rw 0 0..255 adc result of channel 3 after finishing the a to d conversi on the processor is informed by means of an interrupt. the interrupt service routine can now take the conversion result of channel 4 from cadc3. the result will be stable for about 46 ms after the interrupt. cadcco hd5 rw h00 adc configuration adwule hd5[4] rw 0 0..1 defines threshold level for wake up. a special wake up unit has been included to allow a system wake up as soon as the analog input signa l on pin p2.0 drops below a predefined level. adwule defines the threshold level. adwule = 0: threshold level corres ponds to fullscale - 4 lsb. this means that if the digital input value drops below 255 - 4 = 251 an interrupt will be triggered. in voltages that is 2.5 v - 0.039 v = 2.461 v. adwule = 1: threshold level corresponds to fullscale - 16 lsb. this means that if the digital input value drops below 255 - 16 = 239 an interrupt will be triggered. in voltages that is 2.5 v - 0.156 v = 2.344 v. ad[3:0] hd5[3:0] rw 0 0..15 defines whether the corresponding port-pin is used as analog input or as digital input. 0: port pin is digital input (the analog value has less precision). 1: port pin is analog input (t he digital value is always 0). table 3?4: sfr register description, continued name sub dir reset range function .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 129 sfrif psavex hd7 rw h00 power save extra register clk_src hd7[2] rw h00 0 ..1 clock source 0:200 mhz pll (33.33 mhz system clock) selected. 1: pll is bypassed oscillator cl ock 6 mhz (3 mhz system clock selected). in this mode slicer, acquisition, dac and display generator are disabled. pll_res hd7[1] rw h00 0 ..1 pll reset 0:pll not reset. 1:pll reset. pll reset sequence requires that pll_res = 1 for 10 psave hd8 rw hf4 power save register cadc hd8[4] rw 1 0..1 power save cadc 0: power-save mode not started. 1: power-save mode started. in power save mode cadc is disabled but the cadc-wake-up-unit is active. wakup hd8[3] rw 1 0..1 power save cadc-wake-up-unit 0: power-save mode not started. 1: power-save mode started. in power-save mode the cadc-wake-up-unit is disabled. power-save mode of wake up unit is only useful in saving power when cadc bit is set. sli_acq hd8[2] rw 1 0..1 reset xdfp 0: xdfp running 1: xdfp reset disp hd8[1] rw 0 0..1 reset chip 0: no action 1: reset active (resq pin low) peri hd8[0] rw 0 0..1 software reset enable 0: no software reset possible 1: software reset possible table 3?4: sfr register description, continued name sub dir reset range function .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 130 sept. 10, 2004; 6251-556-3ds micronas strvbi hd9 rw h00 configuration acq & slicer acqon hd9[7] rw 0 0..1 enable acquisition: 0: the acq interface does not access memory (immediately inactive). 1: the acq interface is active and writes data to memory (switching on is synchronous to v). reserved hd9[6] rw 0 0..1 config acq & slicer acq_sta hd9[5] rw 0 0..1 first framing code after vertical sync: 0: no framing code after vertical sync has been detected. 1: framing code after vert ical sync has been detected. the bit is set by hardware and cleared by software. vbiadr[3:0] hd9[3:0] rw 0 0..31 defines the 5 msbs of the start address of the vbi buffer (the lsbs are fixed to 0x000). the vbi buffer location can be aligned to any 1 kbyte memory segment. pclk1 hda rw h01 dto pixel frequency factor 1 pf[10:8] hda[3:0] rw 1 0..15 pixel frequency factor (lsbs) this register defines the relation between the output pixel frequency and the frequency of the crystal. the pixel frequency does not depend on the line frequency. it can be calcul ated by the following formula: fpixel = pf * 324 mhz / 8192 the pixel frequency can be adjusted in steps of 36.6 khz. after power-on this register is set to 328d. so, the default pixel frequency is set to 12.97 mhz. attention: register values greater then 983d generate pixel frequencies which are outside of the specified boundaries. pclk0 hdb rw h48 dto pixel frequency factor 0 pf[7:0] hdb[7:0] rw 72 0..255 pixel frequency factor (lsbs) this register defines the relation between the output pixel frequency and the frequency of the crystal. the pixel frequency does not depend on the line frequency. it can be calcul ated by the following formula: fpixel = pf * 324 mhz / 8192 the pixel frequency can be adjusted in steps of 36.6 khz. after power-on this register is set to 328d. so, the default pixel frequency is set to 12.97 mhz. attention: register values greater then 983d generate pixel frequencies which are outside of the specified boundaries. dsync scr1 he1 rw h00 dsync control 1 reserved he1[7] reserved for internal use. must be set to 1 (see section 2.14. on page 109). rgb_g[1:0] he1[6:5] rw used for dac setup purpose (see section 2.14. on page 109) table 3?4: sfr register description, continued name sub dir reset range function .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 131 cor_bl he1[4] rw 3-level contrast reduction output by means of cor_bl the user is ab le to switch the cor signal to a three level signal providing blank and contrast reduction information on pin blank/cor. 0: two level signal for contrast reduction. 1: three level signal; three level signal level0: blank off; cor off. level1: blank off; cor on. level2: blank on; cor off. note: see section 4.10.3. on page 165 for the detailed specification of these levels. vsu[3:0] he1[3:0] rw 0 0..15 vertical set up time the vertical sync signal is internal ly sampled with the next edge of the horizontal sync edge. the phase relation between v and h differs from application to application. to guarant ee (vertical) jitte r free processing of external sync signals, the ve rtical sync impulse can be delayed before it is internally processed. the following formula shows how to delay the external v-sync before it is internally latched and processed. tv_delay = 3.84 us * vsu scr0 he2 rw h00 dsync control 0 rgb_d[1:0] he2[7:6] rw 0 0..3 rgb/cor delay circuitry in some applications of our cust omers the blanking is fed through other devices before it is used as a si gnal to control the multiplexing of video/rgb-mix. these other device s may create a delay of the blank signal. if no special effort is taken, this delay would create a vertical band at the beginning and the end of the active blanking zone. to compensate this, the generated rgb and the cor signals can be delayed by tvt in reference to t he generated blank signal. this delay is always a multiple of the pixel-frequency from zero delay up to 3 times pixel delay: 00: zero delay of rgb/cor-output in reference to blank-output. 01: one pixel delay of rgb/cor- output in reference to blank- output. 10: two pixel delay of rgb/cor-output in reference to blank-output. 11: three pixel delay of rgb/cor-output in reference to blank- output. hp he2[5] rw 0 0..1 h-pin polarity this bit defines the polarity of the h pin (master and slave mode). 0: normal polarity (active high). 1: negative polarity. vp he2[4] rw 0 0..1 v-pin polarity this bit defines the polarity of the v pin (master and slave mode). 0: normal polarity (active high). 1: negative polarity. int he2[3] rw 0 0..1 interlace / non-interlace tvt can either generate an interlaced or a non-interlaced timing (master mode only). interlaced timing can only be created if vlr is an odd number. 0: interlaced timing is generated. 1: non-interlaced timing is generated. table 3?4: sfr register description, continued name sub dir reset range function .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 132 sept. 10, 2004; 6251-556-3ds micronas snc he2[2] rw 0..1 sandcastle sync (slave mode only) to input pins are reserved for synch ronisation. these input pins can be used as two separated sync input s or as one single sync input. if two separated sync inputs is select ed horizontal syncs are fed in at h pin and vertical syncs are fed in a v pin. if one single input pin is selected the h pin is used as a sandcastle input pin. 0: h/v-sync input at h/v pins 1: sancastle input h pin vcs he[1] rw 0..1 video composite sync vcs defines the sync output at pin v (master mode only) 0: at pin v the vertical sync appears 1: at pin v a composite sync si gnal (including equalizing pulses, h- sync and v_sync) is generated (vcs ). the length of the equalizing pulses have fixed values as descri bed in the timing specifications. note: don?t forget to set registers vlr and hpr (64 s) according to your requirements. mast he[0] rw master/slave mode this bit defines the configuration of the sync system (master or slave mode) and also the direction (input/output) of the v, h pins. 0: slave mode. h, v pins are configured as inputs 1: master mode. h, v pins are configured as outputs. note: switching from slave to master mode resets the internal h, v counters in that way, that the phase shift during the switch can be minimized. in slave mode registers vlr and hpr are not used. sdv1 he3 rw h00 dsync v delay 1 sdv[9:8] he3[1:0] rw 0 0..3 vertical sy nc delay (master and slave mode) this register defines the delay (in lines) from the vertical sync to the first line of character display area on the screen. sdv0 he4 rw h20 dsync v delay 0 sdv[7:0] he4[7:0] rw 32 0..255 vertical sync delay (master and slave mode) this register defines the delay (in lines) from the vertical sync to the first line of character display area on the screen. sdh1 he5 rw h00 dsync h delay 1 sdh[11:8] he5[3:0] rw 0 0..15 horizontal sync delay (master and slave mode) this register defines the delay (in pixels) from the horizontal sync to the first pixel characte r display area on the screen. sdh0 he6 rw h48 dsync h delay 0 sdh[7:0] he6[7:0] rw 72 0..255 horizontal sync delay (master and slave mode) this register defines the delay (in pixels) from the horizontal sync to the first pixel characte r display area on the screen. hcr1 he7 rw h0a dsync h clamp end ehcr[7:0] he7[7:0] rw 10 0..255 end of horizontal clamp phase (master and slave mode) this register defines the end of the horizontal clamp phase from the positive edge of the horizontal sync impulse (at normal polarity). the end of clamp phase can be calculated by the following formula: th_clmp_e = 480 ns * ehcr if ehcr is smaller than bhcr the clamp phase will appear during hsync. table 3?4: sfr register description, continued name sub dir reset range function .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 133 hcr0 he9 rw h00 dsync h clamp begin bhcr[7:0] he9[7:0] rw 0 0..255 beginning of hori zontal clamp phase (master and slave mode) this register defines the delay of the horizontal clamp phase from the positive edge of the horizontal sync impulse (normal polarity is assumed). the beginning of clamp p hase can be calculated by the following formula: th_clmp_b = 480 ns * bhcr if ehcr is smaller than bhcr the clamp phase will appear during hsync. bvcr hea rw h00 dsync v clamp begin 1 bvcr[9:8] hea[1:0] rw 0 0..3 beginning of vert ical clamp phase (master and slave mode) this register defines the beginning of the vertical clamp phase from the positive edge of the vertical sync impulse (at normal polarity) in count of lines. if evcr is smaller than bvcr than the clamp phase will appear during vsync. bvcr0 heb rw h00 dsync v clamp begin 0 bvcr[7:0] heb[7:0] rw 0 0..255 beginning of vert ical clamp phase (master and slave mode) this register defines the beginning of the vertical clamp phase from the positive edge of the vertical sync impulse (at normal polarity) in count of lines. if evcr is smaller than bvcr than the clamp phase will appear during vsync. evcr1 hec rw h00 dsync v clamp end 1 evcr[9:8] hec[1:0] rw 0 0..3 end of vertical clamp phase (master and slave mode) this register defines the end of the vertical clamp phase from the positive edge of the vertical sync impul se (at normal polarity) in count of lines. if evcr is set to a value smaller than bvcr than the vertical blanking phase will last over the vertical blanking interval. if evcr is smaller than bvcr than the clamp phase will appear during vsync. evcr0 hed rw h04 dsync v clamp end 0 evcr[7:0] hed[7:0] rw 4 0..255 end of vertical clamp phase (master and slave mode) this register defines the end of the vertical clamp phase from the positive edge of the vertical sync impul se (at normal polarity) in count of lines. if evcr is set to a value smaller than bvcr than the vertical blanking phase will last over the vertical blanking interval. if evcr is smaller than bvcr than the clamp phase will appear during vsync. vlr1 hee rw h02 dsync vertical line 1 odd_ev hee[6] rw 0 0..1 odd/even detection (slave mode only) used as a interface from the har dware odd/even field detection to software. set to 1 for odd fields and to 0 for even fields. table 3?4: sfr register description, continued name sub dir reset range function .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 134 sept. 10, 2004; 6251-556-3ds micronas vsu2[3:0] hee[5:2] rw 0 0..15 vertical set up time 2 (slave mode only) to realize the odd/even detection of a field next to vsu a second vertical setup time vsu2 is defined by the vsu2 register bits. this horizontal delay is used to recognize the vsync to another time than it is recognized at vsu. the field de tection is realized by detecting if in between these two latching-points the vsync is rising or stable: tv_delay2 = 3.84 us * vsu2 if vsync became active for both vsu and vsu2, an odd field is detected. if vsync became active only for vsu an even field is detected: with inverted vsu and vsu2: vl[9:8] hee[1:0] rw 2 0..3 dsync vetical line 1 vlr0 hef rw h71 dsync vertical line 0 vl[7:0] hef[7:0] rw 113 0..255 amount of vertical lines in a frame (master mode only) tvt generates in sync master mode vertical sync impulses. if for example a normal pal timing should be generated, set this register to ?625d? and set the interlace bit to ?0?. the hardware will generate a vertical impulse periodically after 312.5 lines. if a non-interlace picture with 312 lines should be generated, se t this register to ?312? and set the interlace bit to ?1?. the hardware will generate a vertical impulse every 312 lines. a progressive timing can be generated by setting vlr to ?625? and interlace to ?0?. hpr1 hf1 rw h08 dsync horizontal period 1 hpr[11:8] hf1[3:0] rw 8 0..15 horizontal period factor (master mode only) this register allows to adjust the period of the horizontal sync signal. the horizontal period is independent from the pixel frequency and can be adjusted with the following resolution: th-period = hp x 30 ns hpr0 hf2 rw h55 dsync horizontal period 0 hpr[7:0] hf2[7:0] rw 85 0..255 horizontal period factor (master mode only) this register allows to adjust the period of the horizontal sync signal. the horizontal period is independent from the pixel frequency and can be adjusted with the following resolution: th-period = hp x 30 ns table 3?4: sfr register description, continued name sub dir reset range function h v ................ ................ vsu vsu2 vsu vsu2 field generated field signal bei utilization of vsu and vsu2 h v vsu2 vsu vsu2 vsu field generated field signal bei utilization of vsu and vsu2 vsu2 vsu ................ ................ ................ .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 135 display pointarray1_1 hf3 rw h00 display pointer 1 high byte point1[13:8] hf3[7:0] rw 0 0..255 display pointer 1 high byte pointarray1_0 hf4 rw h06 display pointer 1 low byte point1[7:0] hf4[7:0] rw 6 0..255 display pointer 1 low byte pointarray0_1 hf5 rw h00 display pointer 0 high point0[13:8] hf5[7:0] rw 0 0..255 display pointer 0 high byte pointarray0_0 hf6 rw h00 display pointer 1 high point0[7:0] hf6[7:0] rw 0 0..255 display pointer 0 low byte osd_ctrl hf8 rw h00 display osd control en_ld_cur hf8[3] rw 0 0..1 used to avoid the download of the parameter settings of the gdw from the ram to the local di splay generator register bank. 0: download disabled. 1: download enabled. en_dgout hf8[2] rw 0 0..1 used to disable/enable the output of the display generator. if display generator is disabled the rgb outputs of the tvt are set to black and the outputs blank and cor are set to: cor = enablecor blank = enablebla if display generator is enabled the display information rgb, cor and blank is generated according to the parameter settings in the xram. 0: display generator is disabled. 1: display generator is enabled. dis_cor hf8[1] rw 0 0..1 defines the level of the cor output if display generator is disabled. dis_blank hf8[0] rw 0 0..1 defines the level of the bl ank output if display generator is disabled. tap hf9 reserved tap hfa reserved optimized opti0 hfd reserved freqsel(1) hfd[7] rw freqsel(2) hfd[6] rw oscpd hfd[5] rw additional registers cscr0 hdd rw h00 central special control 0 enetclk hdd[5] rw h00 uart baud rate clk source bits enerclk hdd[4] rw h00 selects between 6 mhz and system clock. p4_7_alt hdd[3] rw h00 selects the output function of the port 0: port function is selected 1: port 4.7 alternate function is selected (see vs_oe ) for input port mode or slave mode vs input mode, port must be switched to input mode by writting ?1? to the port latch. table 3?4: sfr register description, continued name sub dir reset range function .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 136 sept. 10, 2004; 6251-556-3ds micronas vs_oe hdd[2] rw h00 0: p4.7 alternate output mode, odd/even selected 1: p4.7 alternate output mode, vertical sync selected see section 2.13. on page 69 register scr0, for vertical sync details o_e_p3_0 hdd[1] rw h00 0: port 3.0 port mode selected 1: port 3.0 works as a odd/even output o_e_pol hdd[0] rw h00 0: odd = 1, even = 0 1: odd = 0, even = 1 note: polarity is true for both p3.0 and p4.7, cscr1 hde rw h00 central special control 1 intsrc1 hde[7) rw h00 0: port 3.3 is the source of the interrupt, 1: ssu is the source of interrupt,(application note: use with sel 0 0), intsrc0 hde[6] rw h00 0: port 3.3 is the source of the interrupt, 1: ssu is the source of interrupt,(application note: use with sel 0 1), enarw hde[3] rw h00 0: port p4.2 and p4.3 function as port pins 1: port 4.2 and p4.3 function as rd and wr signal outputs. a19 _p4_4 hde[2] rw h00 0: pin functions as address line 1: pin function as port a18 _p4_1 hde[1] rw h00 0: pin functions as address line 1: pin function as port a17 _p4_0 hde[0] rw h00 0: pin functions as address line 1: pin function as port table 3?4: sfr register description, continued name sub dir reset range function .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 137 3.5. acq register block index 3.6. acq register index table 3?5: acq block index name page field_parameter 139 line_parameter 141 table 3?6: acq register bits index name page fc3[15:8] 139 fc3[7:0] 139 fc3mask[15:8] 139 fc3mask [7:0] 139 fc1[7:0] 139 agdon 139 afron 139 anoon 139 gdpon 139 gdnon 139 freon 139 noion 139 full 140 noise(0) 140 freattf 140 stab 140 vdok 140 field 140 noise(1) 140 grdon 140 grdsign 141 leofli[11:8] 141 leofli[7:0] 141 dincr[15:8] 141 dincr[7:0] 141 norm[2:0] 141 fcsel[1:0] 141 fc1er 142 vcr 142 mlength[7:5] 142 alength[4:3] 142 clkdiv[2:0] 142 perr[7:2] 143 tlde 143 fcok 143 table 3?6: acq register bits index, continued name page .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 138 sept. 10, 2004; 6251-556-3ds micronas 3.7. acq register address index table 3?7: acq subaddress index sub data bits reset 7 6 5 4 3 2 1 0 h0000 fc3[15:8] h0000 h0001 fc3[7:0] h0000 h0002 fc3mask[15:8] h0000 h0003 fc3mask [7:0] h0000 h0004 fc1[7:0] h0000 h0005 agdon afron anoon gdpon gdnon freon noion full h0000 h0006 noise(0) freattf stab vdok field noise(1) grdon grdsign h0000 h0007 leofli[11:8] h0000 h0008 leofli[7:0] h0000 h000d dincr[15:8] h0000 h000e dincr[7:0] h0000 h000f norm[2:0] fcsel[1:0] fc1er vcr reserved h0000 h0010 mlength[7:5] alength[4:3] clkdiv[2:0] h0000 h00011 perr[7:2] tlde fcok h0000 .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 139 3.8. acq register description table 3?8: acq register description name addr dir sync reset range function field_parameter acqfp0 h0000 rw vs h0000 fc3[15:8] h0000[7:0] rw vs 0 0..255 acqfp1 h0001 rw vs h0000 fc3[7:0] h0001[7:0] rw vs 0 0..255 programmable 16-bit framing code msb corresponds to first received bit of fc acqfp2 h0002 rw vs h0000 fc3mask[15:8] h0002[7:0] rw vs 0 0..255 acqfp3 h0003 rw vs h0000 fc3mask [7:0] h0003[7:0] rw vs 0 0..255 mask for programmable 16-bit framing code msb corresponds to first received bit of fc 0: this bit is checked 1: this bit is don't care acqfp4 h0004 rw vs h0000 fc1[7:0] h0004[7:0] rw vs 0 0..255 programmable 8-bit framing code msb corresponds to first received bit of fc acqfp5 h0005 rw vs h0000 agdon h0005[7] rw vs 0 0..1 automatic group delay compensation 0: automatic compensation off 1: automatic compensation on afron h0005[6] rw vs 0 0..1 automatic frequency depending attenuation compensation 0: automatic compensation off 1: automatic compensation on anoon h0005[5] rw vs 0 0..1 automatic noise compensation 0: automatic compensation off 1: automatic compensation on gdpon h0005[4] rw vs 0 0..1 allpass filter for positive group delay distortion 0: group delay compensation depends on agd_on 1: positive group delay compensation is always on gdnon h0005[3] rw vs 0 0..1 allpass filter for negative group delay distortion 0: group delay compensation depends on agd_on 1: negative group delay compensation is always on freon h0005[2] rw vs 0 0..1 peaking filter to compensate frequency attenuation 0: frequency depending attenuation compensation depends on afre_on 1: frequency depending attenuation compensation is always on noion h0005[1] rw vs 0 0..1 noise detection and compensation 0: noise compensation depends on anoi_on 1: noise compensation is always on .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 140 sept. 10, 2004; 6251-556-3ds micronas full h0005[0] rw vs 0 0..1 full channel mode 0: full channel mode off 1: full channel mode on note: dont forget to reserve enough memory for the vbi buffer and to initialized the appropriate line parameters. acqfp6 h0006 rw vs h0000 noise(0) h0006[7] rw vs 0 0..15 hsync window defines the width of the window for the acceptance of incoming h-sync pulses 0000: +/- 1.92us 0001: +/- 3.84us ... 1111: +/- 30.072us freattf h0006[6] rw vs 0 0..15 precision control for wss-fc-check the value of wss_pre determi nes how error values around edges inside the wss-fram ing-code are accepted. 0: any error acepted 1: 11 errors accepted ... 10: 2 errors accepted 11: 1 error accepted 12: no error accepted stab h0006[5] rw 0 horizontal sync watchdog 0: h-pll is not locked 1: h-pll is locked (written to memory by acq-interface) vdok h0006[4] rw 0 vertical sync watchdog 0: there was no vertical sync during stable horizontal synchronization. 1: there was at least one vertical sync during stable horizontal synchronozation (written to memory by acq-interface) field h0006[3] rw 0 field detector. 0: actual field is 1 1: actual field is 2. (written to memory by acq-interface) noise(1) h0006[2] rw 0 noise and co-c hannel detector of slicer 1. 00: no noise and no co-channel distortion has been detected. 01: no noise but co-channel-distortion has been detected. 10: noise but no co-channel-distortion has been detected. 11: strong noise has been detected. (written to memory by acq-interface) grdon h0006[1] rw 0 group delay detector 0: no group delay distortion detected 1: group delay distortion detected (written to memory by acq_interface) table 3?8: acq register description, continued name addr dir sync reset range function .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 141 grdsign h0006[0] rw 0 group delay detector. 0: if group delay distortion has been detected, it was positive. 1: if group delay distortion has been detected, it was negative. (written to memory by acq-interface) acqfp7 h0007 rw vs h0000 leofli[11:8] h0007[7:4] rw vs 0 0..7 detection threshold for negative group delay measurement 0000: a small negative group delay activates detection ... 0111: strong negative group delay is needed to activate detection acqfp8 h0008 rw vs h0000 leofli[7:0] h0007[3:0] rw vs 0 0..7 detection threshold for positive group delay measurement 0000: a small positive group delay activates detection ... 0111: strong positive group delay is needed to activate detection line_parameter acqlp0 h000d rw hs h0000 dincr[15:8] h000d[7:0] rw hs 0 0..255 data pll frequency select specifies the operating frequency of the d-pll of the data slicer. dincr = fdata * 2**18 / 40.5 mhz acqlp1 h000e rw hs h0000 dincr[7:0] h000e[7:0] rw hs 0 0..255 data pll frequency select (low byte) (refer to acqlp0) acqlp2 h000f rw hs h0000 norm[2:0] h000f[7:5] rw hs 0 most timing signals are closely related to the actual data service used. therefore 3 bits are reserved to specify the timing for the service used in the actual line . (corresponds to slicer 1) normservice 000txt 001reserved 010vps 011wss 100cc 101reserved 110reserved 111no data service fcsel[1:0] h000f[4:3] rw hs 0 there are three different fr aming codes which can be used for each field. the framing c ode used for the actual line is selected with fcsel (co rresponds to slicer 1). fcselfc 00fc1 01fc2 10fc3 11no fc-check table 3?8: acq register description, continued name addr dir sync reset range function .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 142 sept. 10, 2004; 6251-556-3ds micronas fc1er h000f[2] rw hs 0 if this bit is ?1? the fc1 chec k is performed with one bit error tolerance. 0:no error tolerance for fc1-check 1:one bit error tolerance for fc1-check vcr h000f[1] rw hs 0 this bit is used to change the behavior of the d-pll. (corresponds to slicer 1) 0:d-pll tuning is stopped after cri. 1:d-pll is tuned throughout the line. acqlp3 h0010 rw hs h0000 mlength[7:5] h0010[7:5] rw hs 0 for noise suppression reasons a median filter has been introduced after the actual data separation. because of over sampling successive samples could be averaged. therefore an odd number of sliced successive samples is taken and if the majority are ?1? a ?1? is sliced otherwise a ?0?. mlength specifies how many samples are taken. (corresponds to slicer 1) mlengthnumber of samples 0001 0013 0105 0117 1009 10111 11013 11115 alength[4:3] h0010[4:3] rw hs 0 if noise has been detected or if noiseon = 1 the output of the slicing level filter is further averaged by means of an accumulation (arithmetic averaging). alength specifies the number of slicing level fi lter output values used for averaging. the accumulation clock depends on clkdiv. alengthnumber of slicing level output values used for averaging 002 014 108 1116 clkdiv[2:0] h0010[2:0] rw hs 0 the slicing level filter needs to find the dc value of the cvbs during cri. in order to do this it should suppress at least the cri frequency. as diff erent services use different data frequencies the cri frequency will be different as well. therefore the filter characterist ic needs to be shifted. this can be done by using different cloc ks for the filter. the filter itself shows sufficient s uppression for frequencies between 0.0757 clkdivsl clk 0001 note: f s = 33.33 mhz table 3?8: acq register description, continued name addr dir sync reset range function .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 143 acqlp4 h0011 rw hs h0000 perr[7:2] h0011[7:2] rw hs 0 phase error watch dog (detecti on of test line ccir331a or b) the value shows how often in a line the internal pll found strong phase deviations between pll and sliced data. the value can be used to detect test line ccir331a or b. perrp < 32? no test line. perrp > 31? test line ccir331a or b detected. tlde h0011[1] rw hs 0 test line detected (ccir17 or ccir18 or ccir330) 0: no test line of the above mentioned test lines has been detected. 1: the following data has most likely be sliced from a test line and should therefore be ignored. fcok h0011[0] rw hs 0 framing code received 0:no framing code has been detected (no new data has been written to memory). 1:the selected framing code has been detected (new data has been written to memory. table 3?8: acq register description, continued name addr dir sync reset range function .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 144 sept. 10, 2004; 6251-556-3ds micronas 4. specifications 4.1. outline dimensions for psdip52-1 package fig. 4?1: psdip52-1: p lastic s hrink d ual i n-line p ackage, 52 leads, 600 mil ordering code: po weight approximately 5.13 g .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 145 4.2. outline dimensions for psdip52-2 package fig. 4?2: psdip52-2: p lastic s hrink d ual i n-line p ackage, 52 leads, 600 mil ordering code: po weight approximately 5.92 g .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 146 sept. 10, 2004; 6251-556-3ds micronas 4.3. outline dimensions for pmqfp64-1 package fig. 4?3: pmqfp64-1: p lastic m etric q uad f lat p ackage, 64 leads, 14 .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 147 4.4. outline dimensions for plcc84-1 package fig. 4?4: plcc84-1: p lastic l eaded c hip c arrier, 84 leads, 29.4 .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 148 sept. 10, 2004; 6251-556-3ds micronas 4.5. outline dimensions for pmqfp100-1 package fig. 4?5: pmqfp100-1 : p lastic m etric q uad f lat p ackage, 100 leads, 14 .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 149 4.6. pin connections and short descriptions nc = not connected, leave vacant lv = if not used, leave vacant pin no. pin name type connection short description pmqfp 100-1 pmqfp 64-1 psdip 52-1 52-2 plcc 84-1 (if not used) 1 ?? ?? ?? ?? ?? ??? ??? .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 150 sept. 10, 2004; 6251-556-3ds micronas 19 ??? ??? see section on page 155 . 25 13 16 29 p2.1 i/o 26 14 17 30 p2.2 i/o 27 15 18 31 p2.3 i/o 28 ???? ? see section on page 155. ---------- furthermore, this pin can be selected as an odd/even indicator alternatively to p3.0. see section on page 155. pin no. pin name type connection short description pmqfp 100-1 pmqfp 64-1 psdip 52-1 52-2 plcc 84-1 (if not used) .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 151 31 18 21 34 p3.0 i/o port 3 is an 8-bit bidirec- tional i/o port with internal pull-up resistors. port 3 pins that have ?1? written to them are pulled high by the internal pull-up resistros.in that state the pins can be used as inputs. ------------------ to use the alternated func- tions of port 3, the corre- sponding output latch must be programmed to a ?1? for that function to operate. see section on page 155. 32 19 22 35 p3.1 i/o 33 20 23 36 p3.2 i/ o 34 21 24 37 p3.3 i/ o 35 22 25 38 p3.4 i/ o 36 23 26 39 p3.5 i/ o 37 26 27 40 p3.6 i/ o 38 27 28 41 p3.7 i/ o 39 28 29 42 vss ps ground (0 v) 40 29 30 43 vdd 3.3 ps input/output (3.3 v) 41 47 45 44 p1.0 i/ o port 1 is a 8-bit bidirectional multifunction i/o port with internal pull-up resistors. port 1 pins that have ?1? written to them are pulled high by the internal pull-up resistors and in that state can be used as inputs. ---------- port 1 pins have a alter- nated function. see section on page 155. 42 49 46 45 p1.1 i/ o 43 51 47 46 p1.2 i/ o 44 52 48 47 p1.3 i/ o 45 53 49 48 p1.4 i/o 46 54 50 49 p1.5 i/o 47 55 51 50 p1.6 i/o 48 30 31 51 p4.2 i/o port 4 is a bidirectional i/o port with internal pull-up resistors. port 4 pins that have 1 writ- ten to them are pulled high by the internal pull-up resis- tors. in that state, the pins can be used as inputs. ---------- port 4 pins have a alter- nated function. see section on page 155. 49 31 32 52 p4.3 i/o 50 32 33 53 rst i/o a low level on this pin resets the device. an internal pull- up resistor permits power- on reset using only one external capacitor con- nected to v ss . 51 nc not connected. pin no. pin name type connection short description pmqfp 100-1 pmqfp 64-1 psdip 52-1 52-2 plcc 84-1 (if not used) .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 152 sept. 10, 2004; 6251-556-3ds micronas 52 34 34 54 xtal2 i input of the inverting oscilla- tor amplifier. 53 35 35 55 xtal1 o output of the inverting oscil- lator amplifier 54 nc not connected. 55 36 14 56 vssa ps ground for analog compo- nents 56 37 13 57 vdda 2.5 ps supply voltage for analog components. 57 38 38 58 r o red 58 39 39 59 g o green 59 40 40 60 b o blue 60 42 41 61 blank/cor o blanking and contrast reduction. 61 nc not connected. 62 56 52 62 p1.7 i/o port 1 is a 8-bit bidirectional multifunction i/o port with internal pull-up resistors. port 1 pins that have ?1? written to them are pulled high by the internal pull-up resistors and in that state can be used as inputs. ---------- port 1.7 has an alternated function. see section on page 155. 63 nc not connected. 64 wr o control output. indicates a write access to the internal xram. ---------- it can be used as a write strobe for writing data into an external data ram by a movx instruction. ---------- this signal is also available as p4.3 see section on page 155. pin no. pin name type connection short description pmqfp 100-1 pmqfp 64-1 psdip 52-1 52-2 plcc 84-1 (if not used) .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 153 65 rd o control output. indicates a read access to the internal xram. ---------- it can be used for latching data from the data bus into an external data ram by a movx instruction. ---------- this signal is also available as p4.2 see section on page 155. 66 nc not connected. 67 63 a19 i/o after power-on port p4.0, p4.1 and p4.4 work as addi- tional address lines a17 ... a19. see section on page 155 68 64 a18 i/o 69 65 a17 i/o 70 66 a16 o address bus for external program memory or data ram. 71 67 a15 o 72 fl_pgm i all the pins prefix by fl_ are test pins that must be left open. 73 44 42 68 vdd 2.5 ps supply voltage (2.5 v) 74 45 43 69 vss ps ground (0 v) 75 46 44 70 vdd 3.3 ps input/output (3.3 v) 76 71 a14 o address bus for external program memory or data ram: 77 72 a12 o 78 73 a13 o 79 74 a7 o 80 fl_rst i all the pins prefix by fl_ are test pins that must be left open. 81 75 a8 o address bus for external program memory or data ram. 82 76 a6 o 83 77 a9 o 84 78 a5 o 85 79 a11 o 86 80 a4 o pin no. pin name type connection short description pmqfp 100-1 pmqfp 64-1 psdip 52-1 52-2 plcc 84-1 (if not used) .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 154 sept. 10, 2004; 6251-556-3ds micronas 87 ale o address latch enable 88 81 psen o program store enable. it is a control output signal, which is usually connected to oe input line of the exter- nal program memory to enable the data output. 89 82 a3 o address bus for external program memory or data ram. 90 83 a10 o 91 84 vss ps ground (0 v) 92 1 vdd 3.3 ps input/output (3.3 v) 93 2 a2 o address bus for external program memory or data ram. 94 3 a1 o 95 fl_ce i all the pins prefix by fl_ are test pins that must be left open. 96 4 d7 i/o data bus for external mem- ory or data ram. 97 5 a0 o address bus for external program memory or data ram. 98 6 d6 i/o data bus for external mem- ory or data ram. 99 7 d0 i/o 100 8 d5 i/o pin no. pin name type connection short description pmqfp 100-1 pmqfp 64-1 psdip 52-1 52-2 plcc 84-1 (if not used) .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 155 4.7. port alternate functions pin no. pin name type connection short description pmqfp 100-1 pmqfp 64-1 psdip 52-1 52-2 plcc 84-1 (if not used) 24 12 15 28 cadcco(ad0) i alternate function of p2.0 : adc. 25 13 16 29 cadcco(ad1) i alternate function of p2.1 : adc. 26 14 17 30 cadcco(ad2) i alternate function of p2.2 : adc. 27 15 18 31 cadcco(ad3) i alternate function of p2.3 : adc. 31 18 21 34 cscr0(o_e_p3_0 ) i/o alternate function of p3.0 : odd/even indicator 32 19 22 35 port input mode i/o alternate function of p3.1 : external extra interrupt 0 (intx0 )/uart(txd) port output mode i/o alternate funtion of p3.1 : txd 33 20 23 36 port input mode i/o alternate function of p3.2 : interrupt 0 input/timer 0 gate control input (int0 ) 34 21 24 37 port input mode i/o alternate function of p3.3 : interrupt 1 input/timer 1 gate control input (int1 ) 35 22 25 38 port input mode i alternate function of p3.4 : counter 0 input (t0) 36 23 26 39 port input mode i/o alternate function of p3.5 : counter 1 input (t1) or in master mode hs or vcs output 37 27 28 41 port input mode o alternate function of p3.7 : external extra interrupt 1 (intx1 )/uart(rxd) 38 47 45 44 pwme(e0) i/o alternate function of p1.0 : output 8-bit pulse pwm channel 0 39 49 46 45 pwme(e1) i/o alternate function of p1.1 : output 8-bit pulse pwm channel 1 40 51 47 46 pwme(e2) i/o alternate function of p1.2 : output 8-bit pulse pwm channel 2 .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 156 sept. 10, 2004; 6251-556-3ds micronas 41 52 48 47 pwme(e3) i/o alternate function of p1.3 : output 8-bit pulse pwm channel 3 42 53 49 48 pwme(e4 i/o alternate function of p1.4 : output 8-bit pulse pwm channel 4 43 54 50 49 pwme(e5) i/o alternate function of p1.5 : output 8-bit pulse pwm channel 5 44 55 51 50 pwme(e6) i/o alternate function of p1.6 : output 14-bit pulse pwm channel 0 45 56 52 62 pwme(e7) i/o alternate function of p1.7 : output 14-bit pulse pwm channel 1 48 30 31 51 cscr1(enarw) i/o alternate function of p4.2 : read signal 49 31 32 52 cscr1(enarw) i/o alternate function of p4.3 : write signal 62 56 52 62 cscr0(vs_oe , p1_7 _alt) o alternate function of p1.7 : vs output cscr0(vs_oe , p1_7 _alt) o alternate function of p1.7 : oddeven output 67 cscr1(a19 _p4_1) alternate function of p4.4 : port pin 68 64 cscr1(a18 _p4_1) i/o alternate function of p4.1 : port pin 69 65 cscr1(a17 _p4_0) i/o alternate function of p4.0 : port pin pin no. pin name type connection short description pmqfp 100-1 pmqfp 64-1 psdip 52-1 52-2 plcc 84-1 (if not used) .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 157 4.8. pin descriptions pin numbers refer to the pmqfp100-1 package. pin 1, 2, 3, 4, d0, d1, d2, d3 ? xrom ? vdd 2.5 ? vss ? vdd 3.3 ? p0.0, p0.1, p0.2, p0.3, p0.4, p0.5, p0.6, p0.7 ? ene ? stop ? ocf ? extif ? cvbs ? vdda 2.5 ? vssa ? p2.0, p2.1, p2.2, p2.3 ? see section on page 155. pin 28, nc ? hs/ssc ? vs/p4.7 ? see section on page 155. pin 31, 32, 33, 34, 35, 36, 37 ,38, p3.0, p3.1, p3.2, p3.3, p3.4, p3.5, p3.6, p3.7 ? p3.0 : odd/even indicates output. p3.1 : external extra interrupt 0 (intx0 )/uart(txd) p3.2 : interrupt 0 input/timer 0 gate control input (int0 ) p3.3 : interrupt 1 input/timer 1 gate control input (int1 ) p3.4 : counter 0 input (t0) p3.5 : counter 1 input (t1) or in master mode hs or vcs output p3.7 : external extra interrupt 1 (intx1 )/uart(rxd) note: p3.6 mustnot be kept to ?0? during reset, other- wise a testmode will be activated. see section on page 155. pin 41, 42, 43, 44, 45, 46, 47, 62, p1.0, p1.1, p1.2, p1.3, p1.4, p1.5, p1.6, p1.7 ? see section on page 155. pin 48, 49, p4.2, p4.3 ? p4.2 : rd , read line. this signal is the same as the outcoming signal of pin rd available in some pack- ages. p4.3 : wr , write line. thissignal is the same as the out- coming signal of pin wr , which is only available in some packages. see section on page 155. pin 50, rst ? nc ? xtal2 ? .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 158 sept. 10, 2004; 6251-556-3ds micronas pin 53, xtal1 ? nc ? r, g, b ? blank/cor ? nc ? nc ? wr ? see section on page 155. pin 65, rd ? see section on page 155 pin 66, nc ? a16, a17, a18, a19, p4.0, p4.1, p4.4 ? see section on page 155. pin 70, 71, 76, 77, 78, 79, 81, 82,83, 84, 85, 86, 89, 90, 93, 94, 97, a15, a14, a13, a7, a8, a9, a5, a11, a4, a3, a10, a2, a1, a0 ? fl_pgm, fl_rst, fl_ce ? ale ? psen ? d7, d6, d0, d5 ? .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 159 4.9. pin configurations fig. 4?6: pmqfp100-1 package 46 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 25 26 27 28 29 30 56 55 54 53 52 51 47 48 49 50 81 82 83 84 a11 a4 ale psen a3 a10 vss vdd 3:3 v a2 a1 fl_ce d7 a0 d6 d0 d5 p1.5 p1.4 p1.3 p1.2 p1.1 p1.0 vdd 3.3 v vss p3.7 p3.6 p3.5 p3.4 p3.3 p3.2 p3.1 p3.0 d4 d2 d3 xrom vdd 2.5 v vss 2.5 v vdd 3.3 v p0.0 p0.1 d1 p0.2 p0.3 p0.4 p0.5 p0.6 ocf extif cvbs vdda 2.5 v vssa p2.0 p2.1 p2.2 p2.3 nc hs/ssc vs stop ene p0.7 p1.6 p4.2 p4.3 rst a8 a6 a9 a5 sda 55xx a7 a13 a12 a14 vdd 3.3 v vss vdd 2.5 v fl_pgm a15 fl_rst a17 a16 a18 a19 nc p1.7 nc blank/cor b g r vdda 2.5 v vssa nc xtal1 xtal2 nc nc wr rd .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 160 sept. 10, 2004; 6251-556-3ds micronas fig. 4?7: pmqfp64-1 package 49 p1.1 50 nc 51 p1.2 52 p1.3 53 p1.4 54 p1.5 55 p1.6 56 p1.7 57 p0.0 58 p0.1 59 p0.2 60 p0.3 61 p0.4 62 p0.5 63 nc 64 p0.6 rst 32 p4.3 31 p4.2 30 vdd 3.3 v 29 vss 28 p3.7 27 p3.6 26 nc 25 nc 24 p3.5 23 p3.4 22 p3.3 21 p3.2 20 p3.1 19 p3.0 18 vs 17 p1.0 vdd 3.3 v vss vdd 2.5 v nc blank/cor nc nc b g r vdda 2.5 v vssa xtal1 xtal2 nc p0.7 vdd 2.5 v vss vdd 3.3 v nc nc cvbs nc vdda 2.5 v vssa nc p2.0 p2.1 p2.2 p2.3 hs/ssc 12345678910111213141516 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 sda 55xx .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 161 fig. 4?8: psdip52-1 /psdip 52-2 package 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 vdd 2.5 v vss vdd 3.3 v cvbs vdda 2.5 v vssa p2.0 p2.1 p1.7 p1.6 p1.5 p1.4 p1.3 p1.2 p1.1 p1.0 vdd 3.3 v vss vdd 2.5 v blank/cor b g r vdda 2.5 v p2.2 p2.3 hs/ssc vs p3.0 p3.1 p3.2 p3.3 p3.4 p3.5 vssa xtal1 xtal2 rst p4.3 p4.2 vdd 3.3 v vss p3.7 p3.6 sda 55xx .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 162 sept. 10, 2004; 6251-556-3ds micronas fig. 4?9: plcc84-1 package 75767778798081828384123456 7 8 9 10 11 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 g b blan/cor p1.7 a19 a18 a17 a16 a15 fl_pgm vss vdd 3.3 a14 a12 a13 a7 hs/ssc p2.3 p2.2 p2.1 p2.0 vsa vdda 2.5 cvbs p0.7 p0.6 p0.5 p0.4 p0.3 p0.2 p0.1 p0.0 vdd 3.3 vss vdd 2.5 xrom d3 xtal2 xtal1 vssa vdda 2.5 r d7 a0 d6 d0 d5 d1 d4 d2 a1 a2 sda 55xx a6 a9 a5 a11 a4 psen a3 a8 a10 vss vdd 3.3 p3.6 p3.5 p3.4 p3.3 p3.2 p3.1 p3.0 vs p3.7 vss p4.3 p4.2 p1.6 p1.5 p1.4 p1.3 p1.2 rst p1.1 p1.0 vdd 3.3 .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 163 4.10. electrical characteristics 4.10.1. absolute maximum ratings stresses beyond those listed in the ?absolute maximum ra tings? may cause permanent damage to the device. this is a stress rating only. functional operation of the device at these conditions is not implied. exposure to absolute maximum ratings conditions for extended periods will affect device reliability. this device contains circuitry to protect the inputs and ou tputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than abso- lute maximum-rated voltages to this high-impedance circuit. all voltages listed are referenced to ground excepted where noted. all gnd pins must be connected to a low-resistive ground plane close to the ic. symbol parameter pin name limit values unit min max t a ambient temperature psdip52-1, psdip52-2 1) pmqfp64-1 plcc84-1 pmqfp100-1 ?1 ?1 ?1 ?1 ? ? ? .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 164 sept. 10, 2004; 6251-556-3ds micronas 4.10.2. recommended operating conditions functional operation of the device beyond those indica ted in the ?recomended operating conditions/characteris- tics? is not implied and may result in unpredictable behavior , reduce reliability and lifetime of the device. all voltages listed are referenced to ground except where noted. all gnd pins must be connected to a low-resistive ground plane close to the ic. do not insert the device into a live socket. instead, apply power by switching on the external power supply. symbol parameter pin no. limit values unit min typ max t a ambient operating temperature psdip52-1, psdip52-2 1) pmqfp64-1 plcc84-1 pmqfp100-1 0 0 0 0 70 70 70 70 c c c c t c case operating temperature psdip52-1, psdip52-2 1 pmqfp64-1 plcc84-1 pmqfp100-1 15 15 15 15 40 40 40 40 85 85 85 85 c c c c p max maximum power dissipation psdip52-1, psdip52-2 1) pmqfp64-1 plcc84-1 pmqfp100-1 0.6 0.6 0.6 0.6 w vdd33 1..7 supply voltage 3.3 v 3.0 3.3 3.6 v vdd25 1..2 supply voltage 2.5 v 2.25 2.5 2.75 v vdda 1..4 analog supply voltage 2.25 2.5 2.75 v v il input voltage low all ? .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 165 4.10.3. characteristics symbol parameter pin name limit values unit test conditions min. typ. max. supply i 3.3 v digital supply current for 3.3 v domain 0 1 ma digital pins and blank/ cor left open i 2.5 v digital supply current for 2.5 v domain 0 30 ma min: power down mode max: worst case i ana analog power supply current 0.2 65 ma min: power down mode max: adc (20 ma), dac/ pll (45 ma) worse case i idle idle mode supply current (with a/d wake up, rtc and external interrupts) 5 10 ma max: digital core (7 ma) in idle mode, pll (1.5 ma), adc (1.5 ma) i pd power down mode supply current 0 1 ma max: 1 ma adc supply current i sd slow down mode supply current 4 8 ma max: digital (5 ma(, pll (1.5 ma), adc (1.5 ma) - pll sleep mode - <4 ma digital (< 2 ma), dac/pll (< 1 ma), adc (< 1 ma) i/o voltages v il input low voltage all ? ? ? ? crystal oscillator c fb crystal oscillator frequency xin, xout 6.0 ? .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 166 sept. 10, 2004; 6251-556-3ds micronas cvbs-input c p pin capacitance cvbs - - pf - z p input impedance - - 1/m ? rgb-outputs c p load capacitance r, g, b - 20 pf v outpp output voltage swing 0.5 1.2 v available: 0.5 v, 0.7 v, 1.0 v, 1.2 v u offset rgb offset 175 375 mv t rf rise/fall times - 12.5 ns r i load resistance 10 - k ? address bits t r output rise time a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15, ale, psen , rd , wr - 15 ns (10% - 90%) t f output fall time - 15 ns (10% - 90%) c l load capacitance - 50 pf alternate address control lines t r output rise time p4.0, p4.1, p4.2, p4.3, p4.4 - 15 ns (10% - 90%) t f output fall time - 15 ns (10% - 90%) c l load capacitance - 50 pf c i pin capacitance - 10 pf symbol parameter pin name limit values unit test conditions min. typ. max. .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 167 data bits t r output rise time d0, d1, d2, d3, d4, d5, d6, d7 - 15 ns (10% - 90%) t f output fall time - 15 ns (10% - 90%) c l load capacitance - 50 pf c i pin capacitance - 10 pf control bit corbl=0, blank only t r output rise time blank, corbla 8 15 ns (10% - 90%) t f output fall time 8 15 ns (10% - 90%) v i-n output voltage no data insertion (video) 00.4v v i-y output voltage for data insertion 2.4 v dd 3.3 v c l load capacitance - 50 pf control bit corbl=1, blank and cor t r output rise time blank, corbla - 12.5 ns (10% - 90%) t f output fall time - 12.5 ns (10% - 90%) v ic-n output voltage no data insertion no contrast reduction 00.4v- v c-y output voltage for contrast reduction and no data insertion v mmin v mmax vv mmin = 1/3 x v dd 3.3 - 150 mv v mmax = 1/3 x v dd 3.3 + 150 mv v i-y output voltage for data insertion 2.4 v dd 3.3 v- c l load capacitance - 20 pf pure capacity load hsync (slave mode) t r input rise time hsync - 100 ns (10% - 90%) t f input fall time - 100 ns (10% - 90%) v hyst1 input hysteresis 1 200 450 mv hys 1 selected by software v hyst2 input hysteresis 2 25 275 mv hys selected by software t ipwh input pulse width 100 - ns - c i pin capacitance - 10 pf - i i leakage current -1 1 symbol parameter pin name limit values unit test conditions min. typ. max. .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 168 sept. 10, 2004; 6251-556-3ds micronas vsync t r input rise time hsync - 200 ns (10% - 90%) t f input fall time - 200 ns (10% - 90%) t ipwv input pulse width 2/fh - - - t r output rise time - 15 ns (10% - 90%) t f output fall time - 15 ns (10% - 90%) c l load capacitance - 50 pf - c i pin capacitance - 10 pf - v il input low voltage -0.4 0.8 v - v ih input high voltage 2.0 2.6 v - typical vcs timing (master mode) t hpvcs pulse width of h-sync 4.59 4,59 p1.x, p3.x, p4.x t r output rise time p1.x, p3.x, p4.x - 15 ns (10% - 90%) t f output fall time - 15 ns (10% - 90%) c l load capacitance - 50 pf - c i pin capacitance - 10 pf - symbol parameter pin name limit values unit test conditions min. typ. max. .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 169 4.10.4. timings 4.10.4.1. sync fig. 4?10: h/v-sync-timing (sync master mode) fig. 4?11: vcs-tming (sync master mode) vsync hsync t opwh line i line i + 1 line i + 2 t opwv i vcs equalizing pulses horizontal pulses vcs field sync pulses equalizing pulses horizontal pulse t hpvcs t dep t ep t fsp field sync pulses equalizing pulses t hpvcs t hpr t hpr t hpr .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 170 sept. 10, 2004; 6251-556-3ds micronas 4.10.4.2. program memory read cycle fig. 4?12: program memory read cycle t phix 5 6 1 2 3 4 state a psen d valid t plph t pliv t aviv t cyc psen ? pulse ? width t plph 80 ? ns psen ? to ? valid ? instruction ? in t pliv 57.5 ? ns instruction ? hold ? after ? psen t phix 0 ? ns address ? to ? valid ? instruction ? in t aviv 115 ? ns parameter symbol min max frequency ? of ? internal ? clock f sys instruction ? read ? cycle ? time t cyc valid .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 171 4.10.4.3. data memory read cycle fig. 4?13: data memory read cycle t rhdx 5 6 1 2 3 4 state a rd d valid t rlrh t rldv t av dv t cyc rd pulse width t rlrh 170 ns rd to valid data in t rldv 117.5 ns data hold after rd t rhdx 0 ns address to valid data in t avdv 230 ns parameter symbol min max frequency of internal clock f sys data read cycle time t cyc .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 172 sept. 10, 2004; 6251-556-3ds micronas 4.10.4.4. data memory write cycle fig. 4?14: data memory write cycle t whdx 561234 state a wr d t wlwh t wldv t av dv t cyc wr pulse width t wlwh 170 ns wr to data out t wldv 15 ns data hold after wr t whdx 12,5 ns address to valid data out t avdv 135 parameter symbol min max frequency of internal clock f sys data write cycle time t cyc .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 173 4.10.4.5. blank/cor fig. 4?15: output voltage of the combined blan/cor reduction signal fig. 4?16: output voltage for blanking signal undefined undefined vss3 .3 0.4v 1/3vd d 3.3-150 mv 2.4v vdd3.3 t r t r signal range ideal signal t f t f 1 /3vd d3. 3+1 50m v contrast reduction don't care; blank on contrast reduction on ; blank off contrast reduction off; blank off undefined vss3.3 0.4 2.4 v vdd3.3 t r signal range ideal signal blank on ; contrast reduction don't care blank off; contrast reduction don't care .com .com .com .com 4 .com u datasheet
sda 55xx data sheet 174 sept. 10, 2004; 6251-556-3ds micronas 5. applications fig. 5?1: application diagram tvtext pro sda 55xx r (0.5 vpp ...1.2 vpp) g (0.5 vpp ...1.2 vpp) b (0.5 vpp ...1.2 vpp) r g b blank (3.3v) blank/ cor cvbs (1.2 vpp) cvbs 100 nf sandcastle (max. 2.5 v) xtal2 xtal1 hs/sc +3.3 v +2,5 v +2,5 v vdd3.3 vdd2.5 (rgb) vdd2.5 (adc) port 0 port 1 port 2 (max. 2.5 v) port 3 port 4 up to 1mbyte program memory (115 ns) 8 8 4 8 3...6 8 bit data bus address bus +3.3 v rst# psen 6 mhz 2 x 33 pf sda 5550 only .com .com .com .com 4 .com u datasheet
data sheet sda 55xx micronas sept. 10, 2004; 6251-556-3ds 175 intentionally vacant .com .com .com .com 4 .com u datasheet
all information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. any new issue of this data sheet invalidates previous issues. product availability and delivery are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples deliv- ered. by this publication, micronas gmbh does not assume responsibil- ity for patent infringements or other rights of third parties which may result from its use. further, micronas gmbh reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. no part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of micronas gmbh. sda 55xx data sheet 176 sept. 10, 2004; 6251-556-3ds micronas micronas gmbh hans-bunte-strasse 19 d-79108 freiburg (germany) p.o. box 840 d-79008 freiburg (germany) tel. +49-761-517-0 fax +49-761-517-2174 e-mail: docservice@micronas.com internet: www.micronas.com printed in germany order no. 6251-556-3ds 6. data sheet history 1. data sheet: ?sda 55xx tvtext pro?, july 27, 2001, 6251-556-1ds. first release of the data sheet. 2. data sheet: ?sda 55xx tvtext pro?, march 23, 2004, 6251-556-2ds. second release of the data sheet. major changes: ? new revision, completely updated ? outline dimensions, new graphics ? pin configuration, new graphics ? electrical characteristics updated 3. data sheet: ?sda 55xx tvtext pro?, sept. 10, 2004, 6251-556-3ds. third release of the data sheet. major changes: ? new type sda 5577 added to the sda 55xx-family ? absolute maximum ratings: ambient temperature limit value min: ? .com .com .com 4 .com u datasheet

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